Mesa (main): pan/mdg: Fill from TLS before spilling non-SSA nodes

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Module: Mesa
Branch: main
Commit: 31d26ebf1b9d0f819c894aec10c29a44052a995a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=31d26ebf1b9d0f819c894aec10c29a44052a995a

Author: Icecream95 <ixn at disroot.org>
Date:   Mon Jun  7 19:30:02 2021 +1200

pan/mdg: Fill from TLS before spilling non-SSA nodes

Otherwise the data already written to the node will get overwritten.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>

---

 src/panfrost/midgard/midgard_ra.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index ae4f87342e2..110b5c9cd44 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -865,8 +865,14 @@ mir_spill_register(
         /* For special reads, figure out how many bytes we need */
         unsigned read_bytemask = 0;
 
+        /* If multiple instructions write to this destination, we'll have to
+         * fill from TLS before writing */
+        unsigned write_count = 0;
+
         mir_foreach_instr_global_safe(ctx, ins) {
                 read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
+                if (ins->dest == spill_node)
+                        ++write_count;
         }
 
         /* For TLS, replace all stores to the spilled node. For
@@ -899,7 +905,15 @@ mir_spill_register(
 
                                 mir_insert_instruction_after_scheduled(ctx, block, ins, st);
                         } else {
-                                ins->dest = spill_index++;
+                                unsigned dest = spill_index++;
+
+                                if (write_count > 1 && mir_bytemask(ins) != 0xF) {
+                                        midgard_instruction read =
+                                                v_load_store_scratch(dest, spill_slot, false, 0xF);
+                                        mir_insert_instruction_before_scheduled(ctx, block, ins, read);
+                                }
+
+                                ins->dest = dest;
                                 ins->no_spill |= (1 << spill_class);
 
                                 midgard_instruction st =