Mesa (main): radeon/vcn: move calc_dpb_size into create_decoder

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Fri Jun 18 14:34:47 UTC 2021


Module: Mesa
Branch: main
Commit: 796358e2f56b8444f2d422ea14639945be7c709e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=796358e2f56b8444f2d422ea14639945be7c709e

Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date:   Mon Jun 14 13:35:48 2021 -0400

radeon/vcn: move calc_dpb_size into create_decoder

Dpb buffer size calculation should based on the values provided in player's
decoder creation call. db_alignmet should be decided in decoder creation
call as well. Therefore, move db_alignment and dpb buffer size calculation
from rvcn_dec_message_decode to radeon_create_decoder function.

Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11378>

---

 src/gallium/drivers/radeon/radeon_vcn_dec.c | 48 ++++++++++++++---------------
 src/gallium/drivers/radeon/radeon_vcn_dec.h |  2 ++
 2 files changed, 26 insertions(+), 24 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 47c3c6d3f68..ae9afc07900 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -69,7 +69,7 @@
 #define NUM_AV1_REFS   8
 #define NUM_AV1_REFS_PER_FRAME 7
 
-static unsigned calc_dpb_size(struct radeon_decoder *dec, unsigned db_alignment);
+static unsigned calc_dpb_size(struct radeon_decoder *dec);
 static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec);
 static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec);
 static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec,
@@ -1329,15 +1329,15 @@ static void rvcn_dec_message_create(struct radeon_decoder *dec)
 }
 
 static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn_dec_message_decode_t *decode,
-      rvcn_dec_message_dynamic_dpb_t2_t *dynamic_dpb_t2, unsigned db_alignment)
+      rvcn_dec_message_dynamic_dpb_t2_t *dynamic_dpb_t2)
 {
    struct rvcn_dec_dynamic_dpb_t2 *dpb = NULL;
    unsigned width, height, size;
    uint64_t addr;
    int i;
 
-   width = align(decode->width_in_samples, db_alignment);
-   height = align(decode->height_in_samples, db_alignment);
+   width = align(decode->width_in_samples, dec->db_alignment);
+   height = align(decode->height_in_samples, dec->db_alignment);
    size = align((width * height * 3) / 2, 256);
    if (dec->ref_codec.bts == CODEC_10_BITS)
       size = size * 3 / 2;
@@ -1404,8 +1404,8 @@ static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn
 
    decode->decode_flags = 1;
    dynamic_dpb_t2->dpbConfigFlags = 0;
-   dynamic_dpb_t2->dpbLumaPitch = align(decode->width_in_samples, db_alignment);
-   dynamic_dpb_t2->dpbLumaAlignedHeight = align(decode->height_in_samples, db_alignment);
+   dynamic_dpb_t2->dpbLumaPitch = align(decode->width_in_samples, dec->db_alignment);
+   dynamic_dpb_t2->dpbLumaAlignedHeight = align(decode->height_in_samples, dec->db_alignment);
    dynamic_dpb_t2->dpbLumaAlignedSize = dynamic_dpb_t2->dpbLumaPitch *
       dynamic_dpb_t2->dpbLumaAlignedHeight;
    dynamic_dpb_t2->dpbChromaPitch = dynamic_dpb_t2->dpbLumaPitch >> 1;
@@ -1442,7 +1442,6 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
    rvcn_dec_message_drm_t *drm = NULL;
    rvcn_dec_message_dynamic_dpb_t *dynamic_dpb = NULL;
    rvcn_dec_message_dynamic_dpb_t2_t *dynamic_dpb_t2 = NULL;
-   unsigned db_alignment;
 
    header = dec->msg;
    sizes += sizeof(rvcn_dec_message_header_t);
@@ -1529,19 +1528,13 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
 
    decode->bsd_size = align(dec->bs_size, 128);
 
-   db_alignment = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR &&
-                   dec->base.width > 32 && (dec->stream_type == RDECODE_CODEC_VP9 ||
-                   dec->stream_type == RDECODE_CODEC_AV1 ||
-                   dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) ? 64 : 32;
-
    if (!dec->dpb.res && dec->dpb_type != DPB_DYNAMIC_TIER_2) {
-      unsigned dpb_size = calc_dpb_size(dec, db_alignment);
       bool r;
-      if (dpb_size) {
+      if (dec->dpb_size) {
          if (encrypted) {
-            r = si_vid_create_tmz_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT);
+            r = si_vid_create_tmz_buffer(dec->screen, &dec->dpb, dec->dpb_size, PIPE_USAGE_DEFAULT);
          } else {
-            r = si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT);
+            r = si_vid_create_buffer(dec->screen, &dec->dpb, dec->dpb_size, PIPE_USAGE_DEFAULT);
          }
          assert(encrypted == (bool)(dec->dpb.res->flags & RADEON_FLAG_ENCRYPTED));
          if (!r) {
@@ -1642,7 +1635,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
    decode->sc_coeff_size = 0;
 
    decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
-   decode->db_pitch = align(dec->base.width, db_alignment);
+   decode->db_pitch = align(dec->base.width, dec->db_alignment);
 
    if (((struct si_screen*)dec->screen)->info.family >= CHIP_SIENNA_CICHLID &&
        (dec->stream_type == RDECODE_CODEC_VP9 || dec->stream_type == RDECODE_CODEC_AV1 ||
@@ -1688,15 +1681,15 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
    if (dec->dpb_type == DPB_DYNAMIC_TIER_1) {
       decode->decode_flags = 1;
       dynamic_dpb->dpbArraySize = NUM_VP9_REFS + 1;
-      dynamic_dpb->dpbLumaPitch = align(decode->width_in_samples, db_alignment);
-      dynamic_dpb->dpbLumaAlignedHeight = align(decode->height_in_samples, db_alignment);
+      dynamic_dpb->dpbLumaPitch = align(decode->width_in_samples, dec->db_alignment);
+      dynamic_dpb->dpbLumaAlignedHeight = align(decode->height_in_samples, dec->db_alignment);
       dynamic_dpb->dpbLumaAlignedSize =
          dynamic_dpb->dpbLumaPitch * dynamic_dpb->dpbLumaAlignedHeight;
       dynamic_dpb->dpbChromaPitch = dynamic_dpb->dpbLumaPitch >> 1;
       dynamic_dpb->dpbChromaAlignedHeight = dynamic_dpb->dpbLumaAlignedHeight >> 1;
       dynamic_dpb->dpbChromaAlignedSize =
          dynamic_dpb->dpbChromaPitch * dynamic_dpb->dpbChromaAlignedHeight * 2;
-      dynamic_dpb->dpbReserved0[0] = db_alignment;
+      dynamic_dpb->dpbReserved0[0] = dec->db_alignment;
 
       if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
          dynamic_dpb->dpbLumaAlignedSize = dynamic_dpb->dpbLumaAlignedSize * 3 / 2;
@@ -1810,7 +1803,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
       decode->hw_ctxt_size = dec->ctx.res->buf->size;
 
    if (dec->dpb_type == DPB_DYNAMIC_TIER_2)
-      if (rvcn_dec_dynamic_dpb_t2_message(dec, decode, dynamic_dpb_t2, db_alignment))
+      if (rvcn_dec_dynamic_dpb_t2_message(dec, decode, dynamic_dpb_t2))
          return NULL;
 
    return luma->buffer.buf;
@@ -1984,7 +1977,7 @@ static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec)
 }
 
 /* calculate size of reference picture buffer */
-static unsigned calc_dpb_size(struct radeon_decoder *dec, unsigned db_alignment)
+static unsigned calc_dpb_size(struct radeon_decoder *dec)
 {
    unsigned width_in_mb, height_in_mb, image_size, dpb_size;
 
@@ -2101,8 +2094,8 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec, unsigned db_alignment)
             ? (8192 * 4320 * 3 / 2) * max_references
             : (4096 * 3000 * 3 / 2) * max_references;
       else
-         dpb_size = (align(dec->base.width, db_alignment) *
-            align(dec->base.height, db_alignment) * 3 / 2) * max_references;
+         dpb_size = (align(dec->base.width, dec->db_alignment) *
+            align(dec->base.height, dec->db_alignment) * 3 / 2) * max_references;
 
       if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
          dpb_size = dpb_size * 3 / 2;
@@ -2427,6 +2420,13 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
       }
    }
 
+   dec->db_alignment = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR &&
+                   dec->base.width > 32 && (dec->stream_type == RDECODE_CODEC_VP9 ||
+                   dec->stream_type == RDECODE_CODEC_AV1 ||
+                   dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) ? 64 : 32;
+
+   dec->dpb_size = calc_dpb_size(dec);
+
    if (!si_vid_create_buffer(dec->screen, &dec->sessionctx, RDECODE_SESSION_CONTEXT_SIZE,
                              PIPE_USAGE_DEFAULT)) {
       RVID_ERR("Can't allocated session ctx.\n");
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h b/src/gallium/drivers/radeon/radeon_vcn_dec.h
index 253a0a907d7..7ad88aaa8a6 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h
@@ -1080,6 +1080,8 @@ struct radeon_decoder {
    unsigned stream_handle;
    unsigned stream_type;
    unsigned frame_number;
+   unsigned db_alignment;
+   unsigned dpb_size;
 
    struct pipe_screen *screen;
    struct radeon_winsys *ws;



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