Mesa (main): ac/surface: don't set DCC_PIPE_ALIGN modifier bit for gfx10 with 1 RB

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Module: Mesa
Branch: main
Commit: 61a845ca19f7c1d236a7f517108c6ddb3b929c64
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=61a845ca19f7c1d236a7f517108c6ddb3b929c64

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon May 17 10:17:52 2021 -0400

ac/surface: don't set DCC_PIPE_ALIGN modifier bit for gfx10 with 1 RB

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>

---

 src/amd/common/ac_surface.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index c20f9eb24cb..ac130807766 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -300,7 +300,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
 
          if (info->max_render_backends == 1) {
             ADD_MOD(AMD_FMT_MOD | common_dcc |
-                    AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1) |
                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b) |
                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B))