Mesa (main): 25 new commits

Wed Jun 23 17:42:28 UTC 2021

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=078030973bfe8164b529f77d2d68ebbe602e6a2a
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Mon Jun 21 14:50:07 2021 +0200

    ir3/ra: Fix corner case in collect handling
    
    I ran into this when accidentally changing the scheduling order in the
    hl2 trace.
    
    Fixes: 0ffcb19 ("ir3: Rewrite register allocation")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3dc8c5985858db451ca4a2465ccd2b85ffd8f90f
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 17:44:15 2021 +0200

    ir3: Remove IR3_REG_DEST
    
    This was needed because code iterating the regs array needed to know
    what was a destination and what wasn't, but now we have separate srcs
    and dsts arrays so it's not needed.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=def96adaee49bed7473cb21488c19f6ab60ed6d3
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:31:03 2021 +0200

    ir3: Remove regs array
    
    Now that everything is converted over, switch to separate src/dst
    arrays.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=57aeef5c13538b78ad4fa88cfdc812442b64fb77
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:30:08 2021 +0200

    ir3/frontend: Switch to srcs/dsts arrays
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5785abb9ed305167f9eb617bd0880413a74cf08f
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:29:39 2021 +0200

    ir3/opts: Switch to srcs/dsts arrays
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=58fb0a01e17bfbadbe1ebe1acd5b05e6f50a1e91
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:28:14 2021 +0200

    ir3/validate: Switch to srcs/dsts arrays
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=050ec77d1bcd091b8f588d1e14f151398576b8fe
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:28:01 2021 +0200

    ir3/print: Switch to srcs/dsts arrays
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b4990eea65c6d81aa486d88b36dd0641f349ad4
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:27:28 2021 +0200

    ir3/legalize: Switch to srcs/dsts arrays
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=abebc1f53ffd1e8e57de06e4884b7178def2f7f7
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:26:46 2021 +0200

    ir3/array_to_ssa: Switch to srcs/dsts arrays
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd13081e03545664c46de763e0fc4aef787a3c6b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:25:58 2021 +0200

    ir3/parser: Switch to srcs/dsts arrays
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=af48cfc06b69e1d322a533a8b467deebf6630484
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:23:46 2021 +0200

    ir3/ra: Switch to srcs/dsts arrays
    
    RA was manually fiddling with regs to copy over the parallel copy code,
    which has to be done in a different way, but if we switch this all over
    at once it shouldn't be a problem.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3e08327cf85ef0b07c8e4920c168329cf66ec41
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:20:24 2021 +0200

    ir3/core: Switch to srcs/dsts arrays
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=50994eeabff270a1aeccf7c104104d13a2018dfd
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:13:34 2021 +0200

    ir3/sched: Convert to srcs/dsts arrays
    
    Also change the indexing in ir3_delayslots, so it's finally sane! To do
    this we also have to change foreach_ssa_src_n to index srcs instead of
    regs, so that the indexing stays in sync.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=132dfacdcbefdfa7094dee2ec36e6770edb1c8e9
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:12:31 2021 +0200

    freedreno/tests: Convert to srcs/dsts
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bff83fc42b2fbae6a9a96b1eab9936ce6bcb3a21
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 16:11:52 2021 +0200

    freedreno/isa: Convert to srcs/dsts
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=db7814ad56468b7fd5ffb6e8469ade10ae64a4c6
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 14:01:58 2021 +0200

    ir3: Add srcs/dsts arrays to ir3_instruction
    
    Initially these will shadow regs, so that we can transition things
    before getting rid of regs.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=59b9935877ee29a4ad7f83ac6f0753781530f08b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 13:56:11 2021 +0200

    ir3/legalize: Construct branch properly
    
    Don't just yeet stuff into regs without updating regs_count, etc. This
    will break horribly during the transition otherwise.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e93f15d4bc346dd56bdf93d81513768872d8d1fb
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 13:40:56 2021 +0200

    ir3: Add separate src/dst count in ir3_instr
    
    srcs and dsts will be in separate arrays, so we need everything creating
    it to give a separate source and dest max count.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3071e2e93395efeba14204564eac56ce38adfa37
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 13:19:34 2021 +0200

    ir3: Split ir3_reg_create() into ir3_{src,dst}_create()
    
    Right now they are basically the same, but in the future they will
    append to different arrays.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9af795d9b984055042ef4ed33c6d3f2021be778a
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 12:01:18 2021 +0200

    ir3: Make ir3_instruction::address a normal register
    
    This fixes an annoying mismatch in the indices between foreach_ssa_src_n
    and ir3_delayslots(), and lets us remove a bunch of other special cases.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2522f387a3d640b091b5ae2ca69a5e1d23edce99
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Wed Jun 23 17:51:28 2021 +0200

    ir3: Add is_reg_special()
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dce680737ddb200c59c55a8c696114f793757398
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 12:49:05 2021 +0200

    ir3: Validate that ir3_register::instr is correct
    
    Catch the mistake fixed in the previous commit.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef7bc4a2aa6b0a0063a478499f74a85cf3ef1dd1
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Jun 18 12:48:06 2021 +0200

    ir3: Update ir3_register::instr when cloning instructions
    
    We happened to not clone any SSA instructions, but we will once address
    instructions start counting as SSA. Fix this oversight.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f329ba10ae64a6c58d7945d8b1b3f19959878e2
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Jun 17 17:04:41 2021 +0200

    ir3: Split read-modify-write array dests in two
    
    Instructions that operate on an array read the previous state of the
    array, modify it, and write a new array, at least conceptually before
    RA. Previously the same register specified the previous state and acted
    as the new state, but this meant that it was both a source and
    destination which meant that it was getting in the way of splitting up
    sources and destinations. Break out the source into a separate register,
    and use the new tied-src infrastructure to share code with a6xx atomics.
    With this, there are basically no more special cases for arrays in RA.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc649453364dd1ea3a8efff8f3bc4290ba80e34b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Jun 17 15:14:05 2021 +0200

    ir3: Make tied sources/destinations part of the IR
    
    Previously this was hard-coded for a6xx atomic instructions. However
    we'll need a way for array destinations to point to the source with the
    previous value of the array when we split them up. This is conceptually
    the same as tied source/destinations for a6xx atomics, except that array
    writes sometimes won't have a previous value to point to. So move this
    into the IR so that it can be more dynamic. As a bonus we can move the
    knowledge of a6xx atomics out of RA, where it's out-of-place, and into
    the a6xx-specific code that creates them.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>