Mesa (main): broadcom/compiler: add FLAFIRST and FLNAFIRST opcodes

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Module: Mesa
Branch: main
Commit: 87fa5908b3a0a592f2d8136714b78c8366d90de7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=87fa5908b3a0a592f2d8136714b78c8366d90de7

Author: Iago Toral Quiroga <itoral at igalia.com>
Date:   Wed Jun 23 11:18:50 2021 +0200

broadcom/compiler: add FLAFIRST and FLNAFIRST opcodes

We will at least need the former to implement subgroupElect()

Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

---

 src/broadcom/compiler/v3d_compiler.h | 2 ++
 src/broadcom/qpu/qpu_instr.c         | 6 ++++++
 src/broadcom/qpu/qpu_instr.h         | 2 ++
 src/broadcom/qpu/qpu_pack.c          | 4 +++-
 4 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/broadcom/compiler/v3d_compiler.h b/src/broadcom/compiler/v3d_compiler.h
index 51c755c6d56..564d8b9c8df 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -1234,6 +1234,8 @@ VIR_A_ALU1(NEG)
 VIR_A_ALU1(FLAPUSH)
 VIR_A_ALU1(FLBPUSH)
 VIR_A_ALU1(FLPOP)
+VIR_A_ALU0(FLAFIRST)
+VIR_A_ALU0(FLNAFIRST)
 VIR_A_ALU1(SETMSF)
 VIR_A_ALU1(SETREVF)
 VIR_A_ALU0(TIDX)
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index 0bda9a42c51..569c5fc4074 100644
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -137,6 +137,8 @@ v3d_qpu_add_op_name(enum v3d_qpu_add_op op)
                 [V3D_QPU_A_TMUWT] = "tmuwt",
                 [V3D_QPU_A_VPMSETUP] = "vpmsetup",
                 [V3D_QPU_A_VPMWT] = "vpmwt",
+                [V3D_QPU_A_FLAFIRST] = "flafirst",
+                [V3D_QPU_A_FLNAFIRST] = "flnafirst",
                 [V3D_QPU_A_LDVPMV_IN] = "ldvpmv_in",
                 [V3D_QPU_A_LDVPMV_OUT] = "ldvpmv_out",
                 [V3D_QPU_A_LDVPMD_IN] = "ldvpmd_in",
@@ -406,6 +408,8 @@ static const uint8_t add_op_args[] = {
         [V3D_QPU_A_BARRIERID] = D,
         [V3D_QPU_A_TMUWT] = D,
         [V3D_QPU_A_VPMWT] = D,
+        [V3D_QPU_A_FLAFIRST] = D,
+        [V3D_QPU_A_FLNAFIRST] = D,
 
         [V3D_QPU_A_VPMSETUP] = D | A,
 
@@ -930,6 +934,8 @@ v3d_qpu_reads_flags(const struct v3d_qpu_instr *inst)
                 case V3D_QPU_A_VFLNB:
                 case V3D_QPU_A_FLAPUSH:
                 case V3D_QPU_A_FLBPUSH:
+                case V3D_QPU_A_FLAFIRST:
+                case V3D_QPU_A_FLNAFIRST:
                         return true;
                 default:
                         break;
diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index a87ed9ff3a9..cf2576fc70b 100644
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -191,6 +191,8 @@ enum v3d_qpu_add_op {
         V3D_QPU_A_TMUWT,
         V3D_QPU_A_VPMSETUP,
         V3D_QPU_A_VPMWT,
+        V3D_QPU_A_FLAFIRST,
+        V3D_QPU_A_FLNAFIRST,
         V3D_QPU_A_LDVPMV_IN,
         V3D_QPU_A_LDVPMV_OUT,
         V3D_QPU_A_LDVPMD_IN,
diff --git a/src/broadcom/qpu/qpu_pack.c b/src/broadcom/qpu/qpu_pack.c
index 5274077530d..fa3bc87c0ba 100644
--- a/src/broadcom/qpu/qpu_pack.c
+++ b/src/broadcom/qpu/qpu_pack.c
@@ -519,8 +519,10 @@ static const struct opcode_desc add_ops[] = {
         { 187, 187, 1 << 2, 1 << 4, V3D_QPU_A_BARRIERID, 40 },
         { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
         { 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT },
-
+        { 187, 187, 1 << 2, 1 << 7, V3D_QPU_A_FLAFIRST, 41 },
+        { 187, 187, 1 << 3, 1 << 0, V3D_QPU_A_FLNAFIRST, 41 },
         { 187, 187, 1 << 3, ANYMUX, V3D_QPU_A_VPMSETUP, 33 },
+
         { 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_IN, 40 },
         { 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_OUT, 40 },
         { 188, 188, 1 << 1, ANYMUX, V3D_QPU_A_LDVPMD_IN, 40 },