Mesa (main): freedreno+ir3: Enable INT16

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Module: Mesa
Branch: main
Commit: 140ce4f8ede44b743b11772c84d912065174af42
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=140ce4f8ede44b743b11772c84d912065174af42

Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Jun 21 14:21:00 2021 -0700

freedreno+ir3: Enable INT16

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11545>

---

 src/freedreno/ci/traces-freedreno.yml            |  4 ++--
 src/freedreno/ir3/ir3_nir.c                      | 14 ++++++++++++++
 src/gallium/drivers/freedreno/freedreno_screen.c |  2 +-
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/freedreno/ci/traces-freedreno.yml b/src/freedreno/ci/traces-freedreno.yml
index 2d528fcff82..199cf43ec9a 100644
--- a/src/freedreno/ci/traces-freedreno.yml
+++ b/src/freedreno/ci/traces-freedreno.yml
@@ -67,7 +67,7 @@ traces:
       # - device: freedreno-a530
       #   checksum: 1ae49af7017ae2a08fbb1caf377ada91
       - device: freedreno-a630
-        checksum: fede0e29fa22a625be6adbd86e70c8c6
+        checksum: eb89b63087f6f252923f567228035b4b
   - path: 0ad/0ad.trace
     expectations:
       # triggers hangcheck on db410c
@@ -268,7 +268,7 @@ traces:
       - device: freedreno-a306
         checksum: c31e4b18d29e87751e4c30760ddfef18
       - device: freedreno-a530
-        checksum: a68a23264fb802d59c92b3a58753e6a4
+        checksum: 3272ac6018600da9cc61636416ed387e
       - device: freedreno-a630
         checksum: 2570e22fbb4ad1a68b45e4caf682d77d
   - path: glmark2/jellyfish.trace
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 4fdbabb72cc..0f13f5b25ee 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -223,6 +223,20 @@ ir3_optimize_loop(struct ir3_compiler *compiler, nir_shader *s)
 			progress |= OPT(s, nir_opt_gcm, false);
 		progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 		progress |= OPT(s, nir_opt_intrinsics);
+		/* NOTE: GS lowering inserts an output var with varying slot that
+		 * is larger than VARYING_SLOT_MAX (ie. GS_VERTEX_FLAGS_IR3),
+		 * which triggers asserts in nir_shader_gather_info().  To work
+		 * around that skip lowering phi precision for GS.
+		 *
+		 * Calling nir_shader_gather_info() late also seems to cause
+		 * problems for tess lowering, for now since we only enable
+		 * fp16/int16 for frag and compute, skip phi precision lowering
+		 * for other stages.
+		 */
+		if ((s->info.stage == MESA_SHADER_FRAGMENT) ||
+				(s->info.stage == MESA_SHADER_COMPUTE)) {
+			progress |= OPT(s, nir_opt_phi_precision);
+		}
 		progress |= OPT(s, nir_opt_algebraic);
 		progress |= OPT(s, nir_lower_alu);
 		progress |= OPT(s, nir_lower_pack);
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index cfd368db2e4..72fe7112d3a 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -641,9 +641,9 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_INT64_ATOMICS:
    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
    case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
-   case PIPE_SHADER_CAP_INT16:
    case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
       return 0;
+   case PIPE_SHADER_CAP_INT16:
    case PIPE_SHADER_CAP_FP16:
       return (
          (is_a5xx(screen) || is_a6xx(screen)) &&