Mesa (master): radv: don't shrink image stores for The Surge 2
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gitlab-mirror at kemper.freedesktop.org
Wed Mar 3 15:23:35 UTC 2021
Module: Mesa
Branch: master
Commit: 21697082ec92c7c83d03d9dc42c938d3b5f483c3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21697082ec92c7c83d03d9dc42c938d3b5f483c3
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Tue Feb 23 19:33:02 2021 +0000
radv: don't shrink image stores for The Surge 2
The game seems to declare the wrong format.
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Fixes: e4d75c22 ("nir/opt_shrink_vectors: shrink image stores using the format")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4347
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9229>
---
src/amd/vulkan/radv_device.c | 5 +++++
src/amd/vulkan/radv_pipeline.c | 8 +++++---
src/amd/vulkan/radv_private.h | 1 +
src/amd/vulkan/radv_shader.c | 11 ++++++-----
src/amd/vulkan/radv_shader.h | 4 ++--
src/util/00-mesa-defaults.conf | 4 ++++
src/util/driconf.h | 4 ++++
7 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a22352b4a0c..99cafa4ea1c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -885,6 +885,10 @@ radv_handle_per_app_options(struct radv_instance *instance,
driQueryOptionb(&instance->dri_options,
"radv_enable_mrt_output_nan_fixup");
+ instance->disable_shrink_image_store =
+ driQueryOptionb(&instance->dri_options,
+ "radv_disable_shrink_image_store");
+
if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
}
@@ -897,6 +901,7 @@ static const driOptionDescription radv_dri_options[] = {
DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT(false)
DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING(false)
DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP(false)
+ DRI_CONF_RADV_DISABLE_SHRINK_IMAGE_STORE(false)
DRI_CONF_RADV_NO_DYNAMIC_BOUNDS(false)
DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0)
DRI_CONF_SECTION_END
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index be91bb4a561..cdbd42abff7 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2359,7 +2359,8 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders,
if (nir_lower_io_to_scalar_early(ordered_shaders[i], mask)) {
/* Optimize the new vector code and then remove dead vars */
nir_copy_prop(ordered_shaders[i]);
- nir_opt_shrink_vectors(ordered_shaders[i], true);
+ nir_opt_shrink_vectors(ordered_shaders[i],
+ !pipeline->device->instance->disable_shrink_image_store);
if (ordered_shaders[i]->info.stage != last) {
/* Optimize swizzled movs of load_const for
@@ -3305,7 +3306,7 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (nir[i]) {
radv_start_feedback(stage_feedbacks[i]);
- radv_optimize_nir(nir[i], optimize_conservatively, false);
+ radv_optimize_nir(device, nir[i], optimize_conservatively, false);
radv_stop_feedback(stage_feedbacks[i], false);
}
}
@@ -3351,7 +3352,8 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
radv_lower_io(device, nir[i]);
- lower_to_scalar |= nir_opt_shrink_vectors(nir[i], true);
+ lower_to_scalar |= nir_opt_shrink_vectors(nir[i],
+ !device->instance->disable_shrink_image_store);
if (lower_to_scalar)
nir_lower_alu_to_scalar(nir[i], NULL, NULL);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 45677e4018a..eb7b645b11d 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -329,6 +329,7 @@ struct radv_instance {
*/
bool enable_mrt_output_nan_fixup;
bool disable_tc_compat_htile_in_general;
+ bool disable_shrink_image_store;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index dfb23153b58..dd5ee93bbb6 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -172,8 +172,8 @@ void radv_DestroyShaderModule(
}
void
-radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
- bool allow_copies)
+radv_optimize_nir(const struct radv_device *device, struct nir_shader *shader,
+ bool optimize_conservatively, bool allow_copies)
{
bool progress;
unsigned lower_flrp =
@@ -243,7 +243,8 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
}
NIR_PASS(progress, shader, nir_opt_undef);
- NIR_PASS(progress, shader, nir_opt_shrink_vectors, true);
+ NIR_PASS(progress, shader, nir_opt_shrink_vectors,
+ !device->instance->disable_shrink_image_store);
if (shader->options->max_unroll_iterations) {
NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
}
@@ -647,7 +648,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_lower_load_const_to_scalar(nir);
if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
- radv_optimize_nir(nir, false, true);
+ radv_optimize_nir(device, nir, false, true);
/* call radv_nir_lower_ycbcr_textures() late as there might still be
* tex with undef texture/sampler before first optimization */
@@ -710,7 +711,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT) &&
nir->info.stage != MESA_SHADER_COMPUTE) {
/* Optimize the lowered code before the linking optimizations. */
- radv_optimize_nir(nir, false, false);
+ radv_optimize_nir(device, nir, false, false);
}
return nir;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index c2e5878efcf..eee9507428d 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -424,8 +424,8 @@ struct radv_shader_slab {
};
void
-radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
- bool allow_copies);
+radv_optimize_nir(const struct radv_device *device, struct nir_shader *shader,
+ bool optimize_conservatively, bool allow_copies);
bool
radv_nir_lower_ycbcr_textures(nir_shader *shader,
const struct radv_pipeline_layout *layout);
diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf
index 60818d839ce..a559c59ed97 100644
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -742,6 +742,10 @@ TODO: document the other workarounds.
<option name="radv_no_dynamic_bounds" value="true" />
</application>
+ <application name="The Surge 2" application_name_match="Fledge">
+ <option name="radv_disable_shrink_image_store" value="true" />
+ </application>
+
<application name="World War Z" application_name_match="WWZ">
<option name="radv_override_uniform_offset_alignment" value="16" />
</application>
diff --git a/src/util/driconf.h b/src/util/driconf.h
index 84d6765553f..f210ed39355 100644
--- a/src/util/driconf.h
+++ b/src/util/driconf.h
@@ -450,6 +450,10 @@
DRI_CONF_OPT_B(radv_no_dynamic_bounds, def, \
"Disabling bounds checking for dynamic buffer descriptors")
+#define DRI_CONF_RADV_DISABLE_SHRINK_IMAGE_STORE(def) \
+ DRI_CONF_OPT_B(radv_disable_shrink_image_store, def, \
+ "Disabling shrinking of image stores based on the format")
+
#define DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(def) \
DRI_CONF_OPT_I(radv_override_uniform_offset_alignment, def, 0, 128, \
"Override the minUniformBufferOffsetAlignment exposed to the application. (0 = default)")
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