Mesa (master): radv: don't set sx_blend_opt_epsilon for V_028C70_COLOR_10_11_11

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Module: Mesa
Branch: master
Commit: 524848707b4f2635a64b42bff1e530f0d6e0c0cd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=524848707b4f2635a64b42bff1e530f0d6e0c0cd

Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Fri Mar  5 10:58:03 2021 +0000

radv: don't set sx_blend_opt_epsilon for V_028C70_COLOR_10_11_11

Matches radeonsi and PAL. From PAL:
// 1 is recommended, but doesn't provide sufficient precision

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4394
Fixes: ed946381564 ("radv: Enable RB+ where possible.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9427>

---

 src/amd/vulkan/radv_cmd_buffer.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 511bbeeb2c1..5fb2d1a72a6 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1238,10 +1238,8 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 			break;
 
 		case V_028C70_COLOR_10_11_11:
-			if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
+			if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
 				sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
-				sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
-			}
 			break;
 
 		case V_028C70_COLOR_2_10_10_10: