Mesa (master): nir-to-tgsi: Fix handling of partial writemasks on SSA/REG decls.

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Module: Mesa
Branch: master
Commit: f301eec9a39a40e3c03018aa72d662263c4ff54f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f301eec9a39a40e3c03018aa72d662263c4ff54f

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Mar  2 12:10:49 2021 -0800

nir-to-tgsi: Fix handling of partial writemasks on SSA/REG decls.

In nouveau's PBO path with GS support and no VS layer export, we got:

        intrinsic store_output (ssa_1, ssa_0) (0, 15, 0, 160, 128) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */     /* out_pos */
        [...]
        vec3 32 ssa_4 = mov ssa_3.xxx
        intrinsic store_output (ssa_4, ssa_0) (0, 4, 0, 160, 128) /* base=0 */ /* wrmask=z */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 *//* out_pos */

The mov's SSA value we would decide we could store directly to the output,
since nothing else used it.  However, the store has a writemask, and the
ALU op was stomping over it instead of ANDing with the output decl's
existing writemask.

Fixes: f79f382c81f8 ("nir_to_tgsi: Store directly to TGSI outputs when possible.")
Closes: #4380
Tested-by: Ilia Mirkin <imirkin at alum.mit.edu>
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9376>

---

 src/gallium/auxiliary/nir/nir_to_tgsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c
index eb386103f2a..b8060d60f8a 100644
--- a/src/gallium/auxiliary/nir/nir_to_tgsi.c
+++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c
@@ -699,9 +699,9 @@ ntt_emit_alu(struct ntt_compile *c, nir_alu_instr *instr)
       dst.Saturate = true;
 
    if (dst_64)
-      dst.WriteMask = ntt_64bit_write_mask(instr->dest.write_mask);
+      dst = ureg_writemask(dst, ntt_64bit_write_mask(instr->dest.write_mask));
    else
-      dst.WriteMask = instr->dest.write_mask;
+      dst = ureg_writemask(dst, instr->dest.write_mask);
 
    static enum tgsi_opcode op_map[][2] = {
       [nir_op_mov] = { TGSI_OPCODE_MOV, TGSI_OPCODE_MOV },