Mesa (master): intel/fs: Handle payload node interference in destinations

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Module: Mesa
Branch: master
Commit: b9e9f92f73df91e0cb64094170ab3ba7fad16f07
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9e9f92f73df91e0cb64094170ab3ba7fad16f07

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Mar 10 13:19:53 2021 -0600

intel/fs: Handle payload node interference in destinations

Starting with d0d039a4d3f49, we emit writes to the push constant chunk
of the payload to stomp out-of-bounds data to zero for Vulkan.  Then, in
369eab9420cfc, we started emitting shader preamble code for emulated
push constants on Gen12.5 parts.  In either of these cases, we can run
into issues if we don't have a proper live range for some of the payload
registers where they get used for something and then smashed by our push
handling code.  We've not seen many issues with this yet because it only
happens when you have dead push constants.

Fixes: d0d039a4d3f49 "anv: Emit pushed UBO bounds checking code..."
Fixes: 369eab9420cfc "intel/fs: Emit code for Gen12-HP indirect..."
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9501>

---

 src/intel/compiler/brw_fs_reg_allocate.cpp | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp
index 52da2be2745..2706be812c6 100644
--- a/src/intel/compiler/brw_fs_reg_allocate.cpp
+++ b/src/intel/compiler/brw_fs_reg_allocate.cpp
@@ -384,6 +384,16 @@ void fs_visitor::calculate_payload_ranges(int payload_node_count,
          }
       }
 
+      if (inst->dst.file == FIXED_GRF) {
+         int node_nr = inst->dst.nr;
+         if (node_nr < payload_node_count) {
+            for (unsigned j = 0; j < regs_written(inst); j++) {
+               payload_last_use_ip[node_nr + j] = use_ip;
+               assert(node_nr + j < unsigned(payload_node_count));
+            }
+         }
+      }
+
       /* Special case instructions which have extra implied registers used. */
       switch (inst->opcode) {
       case CS_OPCODE_CS_TERMINATE: