Mesa (master): freedreno/registers: Handle typed registers with fields

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 9a5596d6798c587552e26d53fa6f0acbd649f937
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a5596d6798c587552e26d53fa6f0acbd649f937

Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Tue Mar  9 16:00:15 2021 +0100

freedreno/registers: Handle typed registers with fields

When a bitset is "inline" it should act as-if the its fields were
inserted into the register itself. However when initializing the
register's bitfield we weren't doing a deep copy of the inline bitfield,
so if the register defined additional fields then they would get added
to the original inline bitfield and any further registers with the same
type would get them. Fix this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9493>

---

 src/freedreno/registers/gen_header.py | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/freedreno/registers/gen_header.py b/src/freedreno/registers/gen_header.py
index 45b9a3e1aa9..e6776857431 100644
--- a/src/freedreno/registers/gen_header.py
+++ b/src/freedreno/registers/gen_header.py
@@ -105,7 +105,7 @@ class Bitset(object):
 		self.name = name
 		self.inline = False
 		if template:
-			self.fields = template.fields
+			self.fields = template.fields[:]
 		else:
 			self.fields = []
 
@@ -358,7 +358,12 @@ class Parser(object):
 
 	def parse_reg(self, attrs, bit_size):
 		if "type" in attrs and attrs["type"] in self.bitsets:
-			self.current_bitset = self.bitsets[attrs["type"]]
+			bitset = self.bitsets[attrs["type"]]
+			if bitset.inline:
+				self.current_bitset = Bitset(attrs["name"], bitset)
+				self.current_bitset.inline = True
+			else:
+				self.current_bitset = bitset
 		else:
 			self.current_bitset = Bitset(attrs["name"], None)
 			self.current_bitset.inline = True