Mesa (master): anv,genxml: Handle L3SQCREG1_SQGHPCI in GenXML

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Module: Mesa
Branch: master
Commit: 5f192b190fb19d7b6042f1c90a701a0d7c6dfdea
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f192b190fb19d7b6042f1c90a701a0d7c6dfdea

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Thu Mar 11 17:48:03 2021 -0600

anv,genxml: Handle L3SQCREG1_SQGHPCI in GenXML

Technically, this is only one field on IVB but it's two on BYT and so it
makes things easier if we split it for all Gen7.

While we're here, make some of the other fields in L3SQCREG1 Booleans.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9537>

---

 src/intel/genxml/gen7.xml          | 15 +++++++++++----
 src/intel/genxml/gen75.xml         | 14 ++++++++++----
 src/intel/vulkan/genX_cmd_buffer.c | 18 +++++++++---------
 3 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 76e45dc819c..255fd5e7eb1 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -3788,10 +3788,17 @@
   </register>
 
   <register name="L3SQCREG1" length="1" num="0xb010">
-    <field name="Convert DC_UC" start="24" end="24" type="uint"/>
-    <field name="Convert IS_UC" start="25" end="25" type="uint"/>
-    <field name="Convert C_UC" start="26" end="26" type="uint"/>
-    <field name="Convert T_UC" start="27" end="27" type="uint"/>
+    <field name="L3SQ General Priority Credit Initialization" start="20" end="23" type="uint">
+      <value name="SQGPCI_DEFAULT" value="0x7"/>
+      <value name="BYT_SQGPCI_DEFAULT" value="0xd"/>
+    </field>
+    <field name="L3SQ High Priority Credit Initialization" start="16" end="19" type="uint">
+      <value name="SQHPCI_DEFAULT" value="0x3"/>
+    </field>
+    <field name="Convert DC_UC" start="24" end="24" type="bool"/>
+    <field name="Convert IS_UC" start="25" end="25" type="bool"/>
+    <field name="Convert C_UC" start="26" end="26" type="bool"/>
+    <field name="Convert T_UC" start="27" end="27" type="bool"/>
   </register>
 
   <register name="PS_INVOCATION_COUNT" length="2" num="0x2348">
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 28ee348b8e4..cf7ca7d70de 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -4200,10 +4200,16 @@
   </register>
 
   <register name="L3SQCREG1" length="1" num="0xb010">
-    <field name="Convert DC_UC" start="24" end="24" type="uint"/>
-    <field name="Convert IS_UC" start="25" end="25" type="uint"/>
-    <field name="Convert C_UC" start="26" end="26" type="uint"/>
-    <field name="Convert T_UC" start="27" end="27" type="uint"/>
+    <field name="L3SQ General Priority Credit Initialization" start="19" end="23" type="uint">
+      <value name="SQGPCI_DEFAULT" value="0xc"/>
+    </field>
+    <field name="L3SQ High Priority Credit Initialization" start="14" end="18" type="uint">
+      <value name="SQHPCI_DEFAULT" value="0x4"/>
+    </field>
+    <field name="Convert DC_UC" start="24" end="24" type="bool"/>
+    <field name="Convert IS_UC" start="25" end="25" type="bool"/>
+    <field name="Convert C_UC" start="26" end="26" type="bool"/>
+    <field name="Convert T_UC" start="27" end="27" type="bool"/>
   </register>
 
   <register name="PERFCNT1" length="2" num="0x91b8">
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index c50b4afca11..a4867862227 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1885,10 +1885,6 @@ genX(CmdExecuteCommands)(
    genX(cmd_buffer_emit_state_base_address)(primary);
 }
 
-#define IVB_L3SQCREG1_SQGHPCI_DEFAULT     0x00730000
-#define VLV_L3SQCREG1_SQGHPCI_DEFAULT     0x00d30000
-#define HSW_L3SQCREG1_SQGHPCI_DEFAULT     0x00610000
-
 /**
  * Program the hardware to use the specified L3 configuration.
  */
@@ -2011,11 +2007,15 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
                    .ConvertDC_UC = !has_dc,
                    .ConvertIS_UC = !has_is,
                    .ConvertC_UC = !has_c,
-                   .ConvertT_UC = !has_t);
-   l3sqcr1 |=
-      GEN_IS_HASWELL ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
-      devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
-      IVB_L3SQCREG1_SQGHPCI_DEFAULT;
+                   .ConvertT_UC = !has_t,
+#if GEN_IS_HASWELL
+                   .L3SQGeneralPriorityCreditInitialization = SQGPCI_DEFAULT,
+#else
+                   .L3SQGeneralPriorityCreditInitialization =
+                        devinfo->is_baytrail ? BYT_SQGPCI_DEFAULT :
+                                               SQGPCI_DEFAULT,
+#endif
+                   .L3SQHighPriorityCreditInitialization = SQHPCI_DEFAULT);
 
    anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
                    .SLMEnable = has_slm,