Mesa (staging/20.3): anv: fix MI_PREDICATE_RESULT write

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Module: Mesa
Branch: staging/20.3
Commit: 596f3190f4a7f0279e642bdcda329b2aaf0a8293
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=596f3190f4a7f0279e642bdcda329b2aaf0a8293

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Fri Mar  5 13:03:07 2021 +0200

anv: fix MI_PREDICATE_RESULT write

This register is only 32bits.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 1952fd8d2ce905 ("anv: Implement VK_EXT_conditional_rendering for gen 7.5+")
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry-picked from commit 8955d179d3e47982ccd67b8aecb0f5bed73d60b6)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9554>

---

 src/intel/vulkan/genX_cmd_buffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index e3eb376fa5a..15d4b00563e 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -4137,7 +4137,7 @@ emit_draw_count_predicate_with_conditional_render(
    pred = gen_mi_iand(b, pred, gen_mi_reg64(ANV_PREDICATE_RESULT_REG));
 
 #if GEN_GEN >= 8
-   gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_RESULT), pred);
+   gen_mi_store(b, gen_mi_reg32(MI_PREDICATE_RESULT), pred);
 #else
    /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
     * so we emit MI_PREDICATE to set it.