Mesa (master): genxml/gen12: 3D_MODE bits 31:16 are no longer must-be-one

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Module: Mesa
Branch: master
Commit: 16d453da7ff2285566a6b2f3e6dabe09590f3fd0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=16d453da7ff2285566a6b2f3e6dabe09590f3fd0

Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Wed Mar 10 09:54:15 2021 -0800

genxml/gen12: 3D_MODE bits 31:16 are no longer must-be-one

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>

---

 src/gallium/drivers/iris/iris_state.c | 1 +
 src/intel/genxml/gen12.xml            | 5 ++++-
 src/intel/genxml/gen125.xml           | 5 ++++-
 src/intel/vulkan/genX_state.c         | 1 +
 4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 4e354a4ba3d..ed4804f9722 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -915,6 +915,7 @@ gen12_upload_pixel_hashing_tables(struct iris_batch *batch)
 
    iris_emit_cmd(batch, GENX(3DSTATE_3D_MODE), p) {
       p.SubsliceHashingTableEnable = true;
+      p.SubsliceHashingTableEnableMask = true;
    }
 }
 #endif
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 903d6e2a4b6..957b05fdf6e 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -1281,7 +1281,10 @@
     <field name="3D Scoreboard Hashing Mode" start="36" end="36" type="bool"/>
     <field name="Subslice Hashing Table Enable" start="37" end="37" type="bool"/>
     <field name="Slice Hashing Table Enable" start="38" end="38" type="bool"/>
-    <field name="Mask" start="48" end="63" type="mbo"/>
+    <field name="Cross Slice Hashing Mode Mask" start="48" end="49" type="uint"/>
+    <field name="3D Scoreboard Hashing Mode Mask" start="52" end="52" type="bool"/>
+    <field name="Subslice Hashing Table Enable Mask" start="53" end="53" type="bool"/>
+    <field name="Slice Hashing Table Enable Mask" start="54" end="54" type="bool"/>
   </instruction>
 
   <instruction name="3DSTATE_AA_LINE_PARAMETERS" bias="2" length="3" engine="render">
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 589f6161652..375191697de 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -1296,7 +1296,10 @@
     <field name="3D Scoreboard Hashing Mode" start="36" end="36" type="bool"/>
     <field name="Subslice Hashing Table Enable" start="37" end="37" type="bool"/>
     <field name="Slice Hashing Table Enable" start="38" end="38" type="bool"/>
-    <field name="Mask" start="48" end="63" type="mbo"/>
+    <field name="Cross Slice Hashing Mode Mask" start="48" end="49" type="uint"/>
+    <field name="3D Scoreboard Hashing Mode Mask" start="52" end="52" type="bool"/>
+    <field name="Subslice Hashing Table Enable Mask" start="53" end="53" type="bool"/>
+    <field name="Slice Hashing Table Enable Mask" start="54" end="54" type="bool"/>
   </instruction>
 
   <instruction name="3DSTATE_AA_LINE_PARAMETERS" bias="2" length="3" engine="render">
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index e5f1b2b4f87..6cbfd9fa124 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -147,6 +147,7 @@ genX(emit_slice_hashing_state)(struct anv_device *device,
 
    anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {
       p.SubsliceHashingTableEnable = true;
+      p.SubsliceHashingTableEnableMask = true;
    }
 #endif
 }