Mesa (master): intel/tools: Handle GT_MODE in the batch decoder
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Sat Mar 20 17:55:49 UTC 2021
Module: Mesa
Branch: master
Commit: 05e133a84a249190188b7dc47a8daf6d6434a6ee
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=05e133a84a249190188b7dc47a8daf6d6434a6ee
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Mon May 11 15:31:57 2020 -0500
intel/tools: Handle GT_MODE in the batch decoder
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
---
src/intel/common/intel_batch_decoder.c | 41 ++++++++++++++++++++++++++++++++++
src/intel/common/intel_decoder.h | 1 +
2 files changed, 42 insertions(+)
diff --git a/src/intel/common/intel_batch_decoder.c b/src/intel/common/intel_batch_decoder.c
index 0b5020c6211..67c52445a8f 100644
--- a/src/intel/common/intel_batch_decoder.c
+++ b/src/intel/common/intel_batch_decoder.c
@@ -253,6 +253,10 @@ dump_binding_table(struct intel_batch_decode_ctx *ctx, uint32_t offset, int coun
return;
}
+ /* When 256B binding tables are enabled, we have to shift the offset */
+ if (ctx->use_256B_binding_tables)
+ offset <<= 3;
+
if (count < 0) {
count = update_count(ctx, ctx->surface_base + offset,
ctx->surface_base, 1, 8);
@@ -852,6 +856,38 @@ decode_3dstate_slice_table_state_pointers(struct intel_batch_decode_ctx *ctx,
decode_dynamic_state_pointers(ctx, "SLICE_HASH_TABLE", p, 1);
}
+static void
+handle_gt_mode(struct intel_batch_decode_ctx *ctx,
+ uint32_t reg_addr, uint32_t val)
+{
+ struct intel_group *reg = intel_spec_find_register(ctx->spec, reg_addr);
+
+ struct intel_field_iterator iter;
+ intel_field_iterator_init(&iter, reg, &val, 0, false);
+
+ uint32_t bt_alignment;
+ bool bt_alignment_mask = 0;
+
+ while (intel_field_iterator_next(&iter)) {
+ if (strcmp(iter.name, "Binding Table Alignment") == 0) {
+ bt_alignment = iter.raw_value;
+ } else if (strcmp(iter.name, "Binding Table Alignment Mask") == 0) {
+ bt_alignment_mask = iter.raw_value;
+ }
+ }
+
+ if (bt_alignment_mask)
+ ctx->use_256B_binding_tables = bt_alignment;
+}
+
+struct reg_handler {
+ const char *name;
+ void (*handler)(struct intel_batch_decode_ctx *ctx,
+ uint32_t reg_addr, uint32_t val);
+} reg_handlers[] = {
+ { "GT_MODE", handle_gt_mode }
+};
+
static void
decode_load_register_imm(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
{
@@ -866,6 +902,11 @@ decode_load_register_imm(struct intel_batch_decode_ctx *ctx, const uint32_t *p)
fprintf(ctx->fp, "register %s (0x%x): 0x%x\n",
reg->name, reg->register_offset, p[2]);
ctx_print_group(ctx, reg, reg->register_offset, &p[2]);
+
+ for (unsigned i = 0; i < ARRAY_SIZE(reg_handlers); i++) {
+ if (strcmp(reg->name, reg_handlers[i].name) == 0)
+ reg_handlers[i].handler(ctx, p[1], p[2]);
+ }
}
}
}
diff --git a/src/intel/common/intel_decoder.h b/src/intel/common/intel_decoder.h
index 580d59c3a1a..697eb69fce0 100644
--- a/src/intel/common/intel_decoder.h
+++ b/src/intel/common/intel_decoder.h
@@ -240,6 +240,7 @@ struct intel_batch_decode_ctx {
struct intel_spec *spec;
enum intel_batch_decode_flags flags;
+ bool use_256B_binding_tables;
uint64_t surface_base;
uint64_t dynamic_base;
uint64_t instruction_base;
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