Mesa (master): radv: don't reset vertex state params on pipeline bind if reg layout matches

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Wed Mar 31 14:06:14 UTC 2021


Module: Mesa
Branch: master
Commit: 71e39c79fdadf68f24a9ae0efa4c0af5526dafce
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=71e39c79fdadf68f24a9ae0efa4c0af5526dafce

Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date:   Thu Jan 28 11:52:42 2021 -0500

radv: don't reset vertex state params on pipeline bind if reg layout matches

this is unnecessary since the locations will match

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>

---

 src/amd/vulkan/radv_cmd_buffer.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 511f3caf7b6..53d9f873404 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4428,6 +4428,12 @@ void radv_CmdBindPipeline(
 			return;
 		radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
 
+		bool vtx_emit_count_changed = !pipeline ||
+					      !cmd_buffer->state.pipeline ||
+					      cmd_buffer->state.pipeline->graphics.vtx_emit_num !=
+					      pipeline->graphics.vtx_emit_num ||
+					      cmd_buffer->state.pipeline->graphics.vtx_base_sgpr !=
+					      pipeline->graphics.vtx_base_sgpr;
 		cmd_buffer->state.pipeline = pipeline;
 		if (!pipeline)
 			break;
@@ -4436,9 +4442,11 @@ void radv_CmdBindPipeline(
 		cmd_buffer->push_constant_stages |= pipeline->active_stages;
 
 		/* the new vertex shader might not have the same user regs */
-		cmd_buffer->state.last_first_instance = -1;
-		cmd_buffer->state.last_vertex_offset = -1;
-		cmd_buffer->state.last_drawid = -1;
+		if (vtx_emit_count_changed) {
+			cmd_buffer->state.last_first_instance = -1;
+			cmd_buffer->state.last_vertex_offset = -1;
+			cmd_buffer->state.last_drawid = -1;
+		}
 
 		/* Prefetch all pipeline shaders at first draw time. */
 		cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;



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