Mesa (master): intel/compiler: add restrictions related to coarse pixel shading

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Module: Mesa
Branch: master
Commit: 0421690f83741c2214680879bbf565cd2a12ae99
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0421690f83741c2214680879bbf565cd2a12ae99

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Thu Oct 29 15:17:16 2020 +0200

intel/compiler: add restrictions related to coarse pixel shading

v2: Update to BITSET_TEST()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>

---

 src/intel/compiler/brw_fs.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 46a9e7cefc4..a876aa42d0c 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1517,6 +1517,9 @@ fs_visitor::emit_samplemaskin_setup()
 
    fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type));
 
+   /* The HW doesn't provide us with expected values. */
+   assert(!wm_prog_data->per_coarse_pixel_dispatch);
+
    fs_reg coverage_mask =
       fetch_payload_reg(bld, payload.sample_mask_in_reg, BRW_REGISTER_TYPE_D);
 
@@ -9262,6 +9265,15 @@ brw_compile_fs(const struct brw_compiler *compiler,
                                "using SIMD8 when dual src blending.\n");
    }
 
+   if (key->coarse_pixel) {
+      if (prog_data->dual_src_blend) {
+         v8->limit_dispatch_width(8, "SIMD16 coarse pixel shading cannot"
+                                  " use SIMD8 messages.\n");
+      }
+      v8->limit_dispatch_width(16, "SIMD32 not supported with coarse"
+                               " pixel shading.\n");
+   }
+
    if (!has_spilled &&
        v8->max_dispatch_width >= 16 &&
        (!(INTEL_DEBUG & DEBUG_NO16) || params->use_rep_send)) {