Mesa (staging/21.0): radv: fix emitting depth bias when beginning a command buffer

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Module: Mesa
Branch: staging/21.0
Commit: 860be94374082aac3ab874c895454b3160432f3f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=860be94374082aac3ab874c895454b3160432f3f

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Apr 19 08:44:40 2021 +0200

radv: fix emitting depth bias when beginning a command buffer

If depth bias is enabled but zero values used, they were never
emitted to the command buffer because they are equal to the default
values.

Previously, they were always emitted when the bound DS attachment
changed.

This should fix some sort of Z fighting with Dota2 on all GPUs.
This also fixes a different issue (ie. some occlusion queries failures)
on GFX6 because CLEAR_STATE is not used on that chip.

Fixes: 8a47422d977 ("radv: do not scale the depth bias for D16_UNORM depth surfaces")
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10310>
(cherry picked from commit 1d3542694bd26d6a912e558af6421aef8e62758f)

---

 .pick_status.json                | 2 +-
 src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index d66c471ce7e..52577e5742a 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -7249,7 +7249,7 @@
         "description": "radv: fix emitting depth bias when beginning a command buffer",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "8a47422d9778056b2263d5f253fab49dfed91486"
     },
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 61a6d825838..5fd9e20e1fd 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1263,7 +1263,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
          RADV_CMD_DIRTY_DYNAMIC_CULL_MODE | RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
 
    if (!cmd_buffer->state.emitted_pipeline)
-      cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
+      cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY |
+                                 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
 
    if (!cmd_buffer->state.emitted_pipeline ||
        cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=