Mesa (staging/21.0): intel/nir: Set lower txs with non-zero LOD

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Module: Mesa
Branch: staging/21.0
Commit: 6d0ad13bf2cd317db76f0bd385770c0c42ccfe69
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d0ad13bf2cd317db76f0bd385770c0c42ccfe69

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Thu Apr 29 23:05:08 2021 -0500

intel/nir: Set lower txs with non-zero LOD

There's a recently discovered HW bug affecting hardware at least as far
back as Skylake where, if the LOD is out-of-bounds for any SIMD lane,
then garbage may be returned in all SIMD lanes.  The easy solution is to
set lower_txs_lod so that we always have a constant LOD of 0 which we
know a priori is always in-bounds.  Fortunately, not many shaders
actually use textureSize() with LOD.

Shader-db results on Ice Lake:

    total instructions in shared programs: 19948537 -> 19948564 (<.01%)
    instructions in affected programs: 3859 -> 3886 (0.70%)
    helped: 0
    HURT: 7

One of the shaders is in Civilization: Beyond Earth, and the rest are
all in Civilization VI.

Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10538>
(cherry picked from commit 05a37e2422080278a668f048cd8bc7a0e4d5d644)

---

 .pick_status.json            | 2 +-
 src/intel/compiler/brw_nir.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 28426ba8bf3..ca62efc8ca2 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1147,7 +1147,7 @@
         "description": "intel/nir: Set lower txs with non-zero LOD",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": null
     },
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 16b589cd645..bbc30025f0c 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -820,6 +820,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
       .lower_txd_shadow_clamp = true,
       .lower_txd_offset_clamp = true,
       .lower_tg4_offsets = true,
+      .lower_txs_lod = true, /* Wa_14012320009 */
    };
 
    OPT(nir_lower_tex, &tex_options);