Mesa (main): asahi: Pass through "reads tilebuffer?" bit

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Module: Mesa
Branch: main
Commit: dd64463d5f79af00ccd803ae317bd626928fec45
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd64463d5f79af00ccd803ae317bd626928fec45

Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date:   Sun May  9 21:04:38 2021 -0400

asahi: Pass through "reads tilebuffer?" bit

To be determined if there's more to this, but it's the only bit I see
varying with Metal when blending is enabled.

Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10720>

---

 src/asahi/compiler/agx_compile.h      |  3 +++
 src/gallium/drivers/asahi/agx_state.c | 10 +++++++---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/asahi/compiler/agx_compile.h b/src/asahi/compiler/agx_compile.h
index f00434f573e..484d96e6fb9 100644
--- a/src/asahi/compiler/agx_compile.h
+++ b/src/asahi/compiler/agx_compile.h
@@ -80,6 +80,9 @@ struct agx_push {
 struct agx_shader_info {
    unsigned push_ranges;
    struct agx_push push[AGX_MAX_PUSH_RANGES];
+
+   /* Does the shader read the tilebuffer? */
+   bool reads_tib;
 };
 
 #define AGX_MAX_RTS (8)
diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index 53698202de6..a59ce975be1 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -1034,16 +1034,18 @@ demo_rasterizer(struct agx_context *ctx, struct agx_pool *pool)
 }
 
 static uint64_t
-demo_unk11(struct agx_pool *pool, bool prim_lines)
+demo_unk11(struct agx_pool *pool, bool prim_lines, bool reads_tib)
 {
 #define UNK11_FILL_MODE_LINES_1 (1 << 26)
 
 #define UNK11_FILL_MODE_LINES_2 (0x5004 << 16)
 #define UNK11_LINES (0x10000000)
 
+#define UNK11_READS_TIB (0x20000000)
+
    uint32_t unk[] = {
       0x200004a,
-      0x200 | (prim_lines ? UNK11_FILL_MODE_LINES_1 : 0),
+      0x200 | (prim_lines ? UNK11_FILL_MODE_LINES_1 : 0) | (reads_tib ? UNK11_READS_TIB : 0),
       0x7e00000 | (prim_lines ? UNK11_LINES : 0),
       0x7e00000 | (prim_lines ? UNK11_LINES : 0),
 
@@ -1105,12 +1107,14 @@ agx_encode_state(struct agx_context *ctx, uint8_t *out,
    struct agx_ptr zero = agx_pool_alloc_aligned(pool, 16, 256);
    memset(zero.cpu, 0, 16);
 
+   bool reads_tib = ctx->fs->info.reads_tib;
+
    agx_push_record(&out, 0, zero.gpu);
    agx_push_record(&out, 5, demo_unk8(ctx->fs, pool));
    agx_push_record(&out, 5, demo_launch_fragment(pool, pipeline_fragment, varyings, ctx->fs->varying_count + 1));
    agx_push_record(&out, 4, demo_linkage(ctx->vs, pool));
    agx_push_record(&out, 7, demo_rasterizer(ctx, pool));
-   agx_push_record(&out, 5, demo_unk11(pool, is_lines));
+   agx_push_record(&out, 5, demo_unk11(pool, is_lines, reads_tib));
    agx_push_record(&out, 10, agx_pool_upload(pool, ctx->viewport, sizeof(ctx->viewport)));
    agx_push_record(&out, 3, demo_unk12(pool));
    agx_push_record(&out, 2, agx_pool_upload(pool, ctx->rast->cull, sizeof(ctx->rast->cull)));