Mesa (main): broadcom/compiler: consider RT component size when lowering logic ops in Vulkan

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Module: Mesa
Branch: main
Commit: 39c41169ba1998c11d486ef644b904d9f9c6fa02
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=39c41169ba1998c11d486ef644b904d9f9c6fa02

Author: Iago Toral Quiroga <itoral at igalia.com>
Date:   Fri May 14 12:03:35 2021 +0200

broadcom/compiler: consider RT component size when lowering logic ops in Vulkan

In Vulkan we configure our integer RTs to clamp automatically, so with logic
operations we need to be careful and avoid overflows by discarding any bits
that won't fit in the RT component size.

Fixes remaining CTS test failures in:
dEQP-VK.pipeline.logic_op.*

Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10801>

---

 src/broadcom/compiler/v3d_nir_lower_logic_ops.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/broadcom/compiler/v3d_nir_lower_logic_ops.c b/src/broadcom/compiler/v3d_nir_lower_logic_ops.c
index c5c30ab7c71..11782c7348f 100644
--- a/src/broadcom/compiler/v3d_nir_lower_logic_ops.c
+++ b/src/broadcom/compiler/v3d_nir_lower_logic_ops.c
@@ -235,6 +235,22 @@ v3d_emit_logic_op_raw(struct v3d_compile *c, nir_builder *b,
                 nir_ssa_def *dst =
                         v3d_nir_get_swizzled_channel(b, dst_chans, fmt_swz[i]);
                 op_res[i] = v3d_logicop(b, c->fs_key->logicop_func, src, dst);
+
+                /* In Vulkan we configure our integer RTs to clamp, so we need
+                 * to ignore result bits that don't fit in the destination RT
+                 * component size.
+                 */
+                if (c->key->environment == V3D_ENVIRONMENT_VULKAN) {
+                        uint32_t bits =
+                                util_format_get_component_bits(
+                                        c->fs_key->color_fmt[rt].format,
+                                        UTIL_FORMAT_COLORSPACE_RGB, i);
+                        if (bits > 0 && bits < 32) {
+                                nir_ssa_def *mask =
+                                        nir_imm_int(b, (1u << bits) - 1);
+                                op_res[i] = nir_iand(b, op_res[i], mask);
+                        }
+                }
         }
 
         nir_ssa_def *r[4];