Mesa (main): aco: Add load_sbt_amd intrinsic implementation.

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Module: Mesa
Branch: main
Commit: bfe28021888f639f38e6dc8066b532347681fd7b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfe28021888f639f38e6dc8066b532347681fd7b

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Mar 23 02:21:38 2021 +0100

aco: Add load_sbt_amd intrinsic implementation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>

---

 src/amd/compiler/aco_instruction_selection.cpp     | 26 ++++++++++++++++++++++
 .../compiler/aco_instruction_selection_setup.cpp   |  1 +
 2 files changed, 27 insertions(+)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index bb60ca99536..0794ca3596a 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -5067,6 +5067,29 @@ void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
                nir_intrinsic_align_mul(instr), nir_intrinsic_align_offset(instr));
 }
 
+void
+visit_load_sbt_amd(isel_context *ctx, nir_intrinsic_instr *instr)
+{
+   Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
+   Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
+   unsigned binding = nir_intrinsic_binding(instr);
+   unsigned base = nir_intrinsic_base(instr);
+
+   index = as_vgpr(ctx, index);
+
+   Builder bld(ctx->program, ctx->block);
+   Temp desc_base = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.sbt_descriptors));
+   Operand desc_off = bld.copy(bld.def(s1), Operand(binding * 16u));
+   Temp rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), desc_base, desc_off);
+
+   /* If we want more we need to implement */
+   assert(instr->dest.ssa.bit_size == 32);
+   assert(instr->num_components == 1);
+
+   bld.mubuf(aco_opcode::buffer_load_dword, Definition(dst), rsrc, index, Operand(0u), base, false,
+             false, true);
+}
+
 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
 {
    Builder bld(ctx->program, ctx->block);
@@ -8489,6 +8512,9 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
       bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bool_to_vector_condition(ctx, shader_query_enabled));
       break;
    }
+   case nir_intrinsic_load_sbt_amd:
+      visit_load_sbt_amd(ctx, instr);
+      break;
    default:
       isel_err(&instr->instr, "Unimplemented intrinsic instr");
       abort();
diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index a90f7c4e060..1e544a98787 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -804,6 +804,7 @@ void init_context(isel_context *ctx, nir_shader *shader)
                   case nir_intrinsic_load_initial_edgeflag_amd:
                   case nir_intrinsic_load_packed_passthrough_primitive_amd:
                   case nir_intrinsic_gds_atomic_add_amd:
+                  case nir_intrinsic_load_sbt_amd:
                      type = RegType::vgpr;
                      break;
                   case nir_intrinsic_shuffle: