Mesa (main): pan/mdg: Fix spills to TLS
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Tue May 18 19:50:38 UTC 2021
Module: Mesa
Branch: main
Commit: a89bc59980b3ea7b2f03d2994bae7dda689f637f
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a89bc59980b3ea7b2f03d2994bae7dda689f637f
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Tue May 18 14:49:49 2021 -0400
pan/mdg: Fix spills to TLS
LOCAL_STORAGE.zw is workgroup local memory, whereas LOCAL_STORAGE.xy is
thread local memory. Likewise PC_SP.zw is the stack pointer, which is
initialized to (LOCAL_STORAGE.zw + offset) but is modifiable by the
shader. Panfrost doesn't modify the s tack pointer, and the register
allocation logic assumes a zero offset, so let's always spill to thread
local memory = LOCAL_STORAGE.xy, as was intended by Italo's cleanup.
This is visible on any shader that spills. Compute shaders aren't
advertised yet, so WLS will be null, causing a fault like the following
(reproduced on Mali T860 with the glyphy trace):
[15634.148873] panfrost ff9a0000.gpu: Unhandled Page fault in AS0 at VA 0x0000000000000000
Reason: TODO
raw fault status: 0x70003C2
decoded fault status: SLAVE FAULT
exception type 0xC2: TRANSLATION_FAULT_LEVEL2
access type 0x3: WRITE
source id 0x700
[15634.658170] panfrost ff9a0000.gpu: gpu sched timeout, js=0, config=0x3300, status=0x8, head=0x31d4540,
tail=0x31d4540, sched_job=00000000e8101b2e
Fixes: 6a12ea02fee ("pan/mdg: properly encode/decode ldst instructions")
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10866>
---
src/panfrost/midgard/compiler.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index 828464a26a5..310032823c3 100644
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -574,7 +574,7 @@ v_load_store_scratch(
.load_store = {
/* For register spilling - to thread local storage */
.arg_reg = REGISTER_LDST_LOCAL_STORAGE_PTR,
- .arg_comp = COMPONENT_Z,
+ .arg_comp = COMPONENT_X,
.bitsize_toggle = true,
.index_format = midgard_index_address_u32,
.index_reg = REGISTER_LDST_ZERO,
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