Mesa (main): isl: Work around NVIDIA and AMD display pitch requirements

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Module: Mesa
Branch: main
Commit: a3a4517f4147a0a7c1b34a4bcd42de45d552df5f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3a4517f4147a0a7c1b34a4bcd42de45d552df5f

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu May 20 02:03:07 2021 -0700

isl: Work around NVIDIA and AMD display pitch requirements

In the case where we're rendering on the Intel GPU, but displaying
on an AMD and NVIDIA GPU, we need to follow their pitch requirements
for our linear scanout buffers.

Based on a patch by Lionel Landwerlin.

Closes: #4706
Reviewed-by: Emma Anholt <emma at anholt.net>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10895>

---

 src/intel/isl/isl.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 2cee638e976..232bd95e065 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1466,9 +1466,12 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev,
     * PRI_STRIDE Stride (p1254):
     *
     *    "When using linear memory, this must be at least 64 byte aligned."
+    *
+    * However, when displaying on NVIDIA and recent AMD GPUs via PRIME,
+    * we need a larger pitch of 256 bytes.  We do that just in case.
     */
    if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
-      alignment = isl_align(alignment, 64);
+      alignment = isl_align(alignment, 256);
 
    return alignment;
 }