Mesa (main): ac: ac_gpu_info::has_vgt_flush_ngg_legacy_bug

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Module: Mesa
Branch: main
Commit: 726cb2d6f6444e3e6a3ccdc7b9197f1c304279aa
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=726cb2d6f6444e3e6a3ccdc7b9197f1c304279aa

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri May 21 08:50:24 2021 +0200

ac: ac_gpu_info::has_vgt_flush_ngg_legacy_bug

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10911>

---

 src/amd/common/ac_gpu_info.c                    | 6 ++++++
 src/amd/common/ac_gpu_info.h                    | 1 +
 src/amd/vulkan/radv_cmd_buffer.c                | 3 +--
 src/gallium/drivers/radeonsi/si_state_shaders.c | 2 +-
 4 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 120dc10bec0..c4a5bf48d06 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -892,6 +892,12 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
     */
    info->has_two_planes_iterate256_bug = info->chip_class == GFX10;
 
+   /* GE has a bug when a legacy GS draw follows an NGG draw and it requires
+    * a VGT_FLUSH to fix that.
+    */
+   info->has_vgt_flush_ngg_legacy_bug = info->chip_class == GFX10 ||
+                                        info->family == CHIP_SIENNA_CICHLID;
+
    /* Support for GFX10.3 was added with F32_ME_FEATURE_VERSION_31 but the
     * firmware version wasn't bumped.
     */
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 7eb9c944d9a..65a4d1adf9e 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -78,6 +78,7 @@ struct radeon_info {
    bool has_zero_index_buffer_bug;
    bool has_image_load_dcc_bug;
    bool has_two_planes_iterate256_bug;
+   bool has_vgt_flush_ngg_legacy_bug;
    bool has_32bit_predication;
    bool has_3d_cube_border_color_mipmap;
 
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3aaa55efca0..1ac322ab18a 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4376,8 +4376,7 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
       /* Prefetch all pipeline shaders at first draw time. */
       cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
 
-      if ((cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 ||
-           cmd_buffer->device->physical_device->rad_info.family == CHIP_SIENNA_CICHLID) &&
+      if (cmd_buffer->device->physical_device->rad_info.has_vgt_flush_ngg_legacy_bug &&
           cmd_buffer->state.emitted_pipeline &&
           radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
           !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index edb5d306014..6ce4b2db349 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -3099,7 +3099,7 @@ bool si_update_ngg(struct si_context *sctx)
        * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
        * pointers are set.
        */
-      if ((sctx->chip_class == GFX10 || sctx->family == CHIP_SIENNA_CICHLID) && !new_ngg) {
+      if (sctx->screen->info.has_vgt_flush_ngg_legacy_bug && !new_ngg) {
          sctx->flags |= SI_CONTEXT_VGT_FLUSH;
          if (sctx->chip_class == GFX10) {
             /* Workaround for https://gitlab.freedesktop.org/mesa/mesa/-/issues/2941 */