Mesa (staging/21.1): 45 new commits
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Thu May 27 11:26:05 UTC 2021
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2bdd37ba3841c9bd21ce7839e913dc484fecf8e
Author: cheyang <cheyang at bytedance.com>
Date: Wed May 26 20:44:57 2021 +0800
virgl:Fix the leak of hw_res used as fence
Fence destroy hw_res not dec reference.Lead leak.
Call virgl_drm_resource_reference() to release hw_res
instead of calling virgl_hw_res_destroy() directly.
Fixes: c54fb6ef3d8 ("virgl: Don't destroy resource while it's in use.")
Signed-off-by: cheyang <cheyang at bytedance.com>
Reviewed-by: Chia-I Wu <olvaffe at gmail.com>
Reviewed-by: Lepton Wu <lepton at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11008>
(cherry picked from commit 4a3c715bb4654ae2c8b61bfb8af8dadde60d675a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f336d95d92d33886476509e4837c16b02e429823
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon May 24 10:56:12 2021 -0700
intel/gfx12+: Add Wa_14013840143
Cc: mesa-stable
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10984>
(cherry picked from commit 6bb66b78a9b252cd344c9c4fd78260f59bbd7b7a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d86c1937d1bf6f013644792cf26e82c5f86a170
Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date: Wed May 26 10:11:01 2021 -0400
zink: remove weird lod hack for texturing
this breaks texturing in non-fragment stages and is unnecessary
due to using nir_lower_tex
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11007>
(cherry picked from commit a9d3b0050251821d3c2571fa310fc8030a7e9e72)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa29e52067a6c0cd46086b19fc5cf03a429950c3
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Mon May 24 15:39:34 2021 +0100
radv: workaround incorrect depthBiasConstantFactor by Path of Exile
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4677
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10980>
(cherry picked from commit 4e4dd4f842929b891e4194e9678d365f08647a87)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5b414ce950a47ae4a5952476570621918f7f595
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Mon May 24 16:23:59 2021 +0100
radv: add radv_absolute_depth_bias
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10980>
(cherry picked from commit 665f11e82939dc8937955f53157b15405a46378a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1b937baa0f658a5bea89b50de69756575070a7c
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon May 24 17:05:30 2021 +0200
aco: fix emitting discard when the program just ends
For fragment shaders that only contain a discard, the exec mask has
to be zero'd and everything discarded.
It seems unnecessary to emit an export here because if the FS has no
exports, the compiler already emits a null export at the end.
Fixes incorrect hair rendering in Detroit: Become Human.
fossil-db (Sienna Cichlid):
Totals from 3 (0.00% of 149839) affected shaders:
CodeSize: 2896 -> 2872 (-0.83%)
Instrs: 556 -> 553 (-0.54%)
Latency: 29266 -> 29214 (-0.18%)
InvThroughput: 3374 -> 3372 (-0.06%)
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10955>
(cherry picked from commit 729ebe4b17f0905f87f41c0ffe004e042f3c55f6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf1b654b6eed185f4541e543445862f3d8f857b4
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Feb 17 14:49:11 2021 -0800
intel/isl: Fix HiZ+CCS comment about ambiguates
Note that CCS isn't ambiguated during a HiZ ambiguate. Dumping the CCS
surface after a HiZ ambiguate shows that the CCS is unchanged.
Fixes: 98dc7f56b7d ("intel/isl: Add a separate ISL_AUX_USAGE_HIZ_CCS_WT")
Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9112>
(cherry picked from commit 19a8bd4c6320e1fefa060e96738835beb24d3209)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eea5538daa9f3cdce9e4ef3dab576e285c8e9744
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri May 21 14:55:26 2021 -0700
anv,iris: Port the D16 workaround stalls to BLORP
Commit cd40110420b added stalls before register writes that occur when
drivers emit depth stencil packets. However, it only did so for
non-BLORP draw calls. Since those packets are sometimes emitted during
BLORP calls, add stalls there too.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4574
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10939>
(cherry picked from commit 34dbbfdd14e5d9501c9a83b52d869cf8b3234f44)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8786b86a440b232ffb00dd935f9f3be6e5dd58ea
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 20 05:05:15 2021 -0400
radeonsi: disable DFSM on gfx9 by default because it decreases performance a lot
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
(cherry picked from commit 56a450e984226640391a8bdef29e16be38fd75cf)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9dfc038dbd865b17c70cef57673a521090cb4243
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed May 12 23:21:36 2021 -0400
radeonsi: add a gfx10 hw bug workaround with the barrier before gs_alloc_req
Fixes: 8845a23698c - amd: add NAVI10 PCI IDs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
(cherry picked from commit 64b75cc12e09dcdafbe205cbf355cd8dfbc7a660)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b0580bdda063a2f281c52d37292187039ce7a8a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Apr 27 23:51:24 2021 -0400
ac/gpu_info: set has_zero_index_buffer_bug for Navi12 too
Acked-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Cc: mesa-stable at lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
(cherry picked from commit 38d3c4251d3fe69667727fcbd11d5fc200ce0fec)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ec8c4d3ab817e738418e1213a9f310b579c374e
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Mon May 24 11:07:11 2021 -0400
panfrost: Increase tiler_heap max allocation to 64MB
We previously allocated only 16MB, but this isn't always enough. Now
that we have growable (heap) on recent kernels, there's not much reason
to try to shrink this allocation.
Fixes OUT_OF_MEMORY fault on furmark trace.
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
(cherry picked from commit ac1ee2bebe19f7d2264325a182b6e84df5db1d16)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=995806af2d260c2f6e8dad07863fe631ab845578
Author: Eric Engestrom <eric at engestrom.ch>
Date: Thu May 27 13:18:27 2021 +0200
.pick_status.json: Update to 3179daf61393ee8a0fac943b94335b114e34873b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa3c13f5a8bdbb50e804bb98c59afe17c6ec1ef1
Author: Italo Nicola <italonicola at collabora.com>
Date: Tue May 11 10:29:01 2021 +0000
panfrost: fix GL_EXT_multisampled_render_to_texture regression
Signed-off-by: Italo Nicola <italonicola at collabora.com>
Fixes: ff3eada7eb4 ("panfrost: Use the generic preload and FB helpers in the gallium driver")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10962>
(cherry picked from commit c746747cb82f10fb5f1f3b625e5833d8d2c1e042)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e8e36e02e20dd52c2ad888d1ea380d1bdbcfedb
Author: Icecream95 <ixn at disroot.org>
Date: Sun May 23 07:10:19 2021 +1200
panfrost: Fix polygon list size computations
As noted in f5c293425fa ("panfrost: Correct polygon size computations"),
"We do have to be careful to add the header size to total comptued BO
size."
Fixes: ff3eada7eb4 ("panfrost: Use the generic preload and FB helpers in the gallium driver")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4660
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4737
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10943>
(cherry picked from commit fe9d37b0c6e89f11a5f25022a851da81d19dab73)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=87019cb375cf6d5bb21665694dae671978d98961
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Apr 29 11:51:14 2021 +0200
radv: fix fast clearing DCC if one level can't be compressed on GFX10+
Fallback to a slow clear, this could be improved by splitting the
clear into two parts (one fast and one slow) but that's complicated.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10516>
(cherry picked from commit e98c61e9f33d3ab8d07f950af3f248554ac2d835)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dff0aa74141ede31c9d92f499d8a62c66f70cb3
Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date: Mon May 10 16:13:01 2021 -0400
aux/trace: fix set_inlinable_constants hook
need to dump the arg, not just the array
Fixes: 8926c4a313e ("aux/trace: add a set_inlinable_constants hook")
Reviewed-by: Adam Jackson <ajax at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10899>
(cherry picked from commit dce827f69c6163c6390f3d561024356d8a50d16e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01185febe4400c013ab70870bb91c76b8f4b2fa8
Author: Robert Tarasov <tutankhamen at chromium.org>
Date: Thu May 20 19:48:16 2021 -0700
iris: Check data alignment for copy_mem_mem
Check both source and destination offsets are aligned to 4. This
patch fixes dEQP-GLES{2|3}.functional.buffer.write.random.* tests
failures on guest side while trying to copy small (<16b) buffers
via glBufferSubData() with offset which isn't aligned to 4.
Fixes: 9b1b9714 ("iris: Use MI_COPY_MEM_MEM for tiny resource_copy_region calls.")
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Lionel Landwerlin lionel.g.landwerlin at intel.com
Reviewed-by: Marcin Ślusarz marcin.slusarz at intel.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10910>
(cherry picked from commit a04d0a304ab9d7f84bd21643cd93584d1dc23adc)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3dc91ff4b50e6082107433e7017a3aef9127da33
Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date: Fri May 21 10:08:01 2021 -0400
aux/vbuf: prevent uint underflow and assert if no vbs are dirty
if this mask is 0, there is nothing to do here
Fixes: e73bf3b805d ("gallium: add start_slot parameter to set_vertex_buffers")
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10929>
(cherry picked from commit 43abed919e21fdca7bf228b573fc25e92a9944e1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=df133b6c864b8ca8e63baa88fb87498f447e668a
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date: Fri May 21 12:36:23 2021 +0200
vc4: initialize array
This fixes a (rather false) error about accessing an array that it is
uninitialized.
Fixes: 7bc39c8418e ("vc4: Add a dump-the-surface-contents routine.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4816
Cc: mesa-stable
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10918>
(cherry picked from commit 7e767ffeb36a7a1de22a73eebca8d7c10034313d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf1c9528864b84992a3dbda437104a0af48c5fe9
Author: SureshGuttula <suresh.guttula at amd.corp-partner.google.com>
Date: Mon May 17 14:22:48 2021 +0530
frontends/va/picture:Fix wrong reallocation even surface is protected
This patch will avoid reallocation,if surface is already protected.
Fixing the comparision logic of boolean value(true \ flase) with
PIPE_BIND_PROTECTED.
Fixes: 81be8b3c2f2 ("va/picture: make sure destination buffer is protected if needed")
Signed-off-by: SureshGuttula <suresh.guttula at amd.corp-partner.google.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10916>
(cherry picked from commit 0236b8a5de9aaffc8bc442a583672453fbc24df4)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6327f49a0bb5253174373f57d29d91d28f988c8
Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date: Tue May 18 19:55:01 2021 -0400
util/prim_restart: fix util_translate_prim_restart_ib
this was broken for the indirect case if the indirect draw count or
firstIndex was nonzero and also would rewrite the index buffer onto the
wrong offset of the dst buffer
Fixes: 0c85d6c523f ("gallium/util: factor out primitive-restart rewriting logic")
Fixes: 330d0607ed6 ("gallium: remove pipe_index_buffer and set_index_buffer")
Reviewed-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10909>
(cherry picked from commit 1272c2e05246cad647324ffdccf56435b97dec1c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=90b63f384ca3e546c47dba7de827dd129c714a3a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu May 20 13:04:15 2021 -0700
iris: Don't advertise Y-tiled modifiers for scanout buffers on Gfx8
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with PIPE_BIND_SCANOUT set,
which we can't support. That led to crashes later when we tried to
create such an image, and isl rightly denied it.
Fixes crashes in wflinfo since c03e79d7831f, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes: c03e79d7831 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
(cherry picked from commit dd508b2bed30901e9dcdd8abb271b5bc28574264)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1363d4f2d8b8edea12d1f86dd1cb0e90296986c3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu May 20 13:04:15 2021 -0700
i965: Don't advertise Y-tiled modifiers for scanout buffers on Gfx8-
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with __DRI_IMAGE_USE_SCANOUT
set, which we can't support. That led to crashes later when we tried
to create such an image, and isl rightly denied it.
This duplicates a bit of code from ISL, but the isl_gfx6_filter_tiling
function that we ought to use to filter things relies on surf_info,
which we don't have at this stage. This is probably good enough.
Fixes crashes in wflinfo since c03e79d7831f, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes: c03e79d7831 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
(cherry picked from commit e9e953ff943475806079d949b37974ce7e63c556)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=568a8ebc8b2be963eb2db64a8aca123c381ec6a7
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 12 10:51:15 2020 -0700
i915g: Stop advertising support for indirect addressing in the FS.
This hardware can't do any form of indirect addressing. The couple of new
Crashes are the backend falling over when faced with loops/ifs.
Fixes: 8a22064d316e ("i915g: Implement vertex textures.")
Reviewed-by: Adam Jackson <ajax at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
(cherry picked from commit 8b0901c70705c1b5f47b17f8c8a7c1150c293362)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67168688b170f63235e101cfad8d78458305b4bc
Author: Emma Anholt <emma at anholt.net>
Date: Tue May 18 10:07:11 2021 -0700
i915g: Add support for the .Absolute flag on TGSI srcs.
We don't have a way to ask TGSI to not have .Absolute, so lower it in the
backend.
Cc: mesa-stable
Reviewed-by: Adam Jackson <ajax at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
(cherry picked from commit 15f608582ec04420213195a0069ca9d83fcd2463)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=139205debacb84fbf787a539d581eced7f259d0f
Author: Emma Anholt <emma at anholt.net>
Date: Mon May 17 11:33:26 2021 -0700
i915g: Disable 3D-pipeline clears.
The 3D-pipeline fast clears try to emit FS constants before an FS is
necessarily bound, causing segfaults in dEQP. Plus it flushes the whole
batchbuffer so it'll probably be slower anyway.
Fixes: 6358e6371b31 ("i915g: implement hw clear")
Reviewed-by: Adam Jackson <ajax at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
(cherry picked from commit 8509aceb7449c6ae0bbc3d35c13a05b62fd48bc1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=af2327b32b7e3716f9a5a70b64ed58aed9a13c7e
Author: Georg Lehmann <dadschoorse at gmail.com>
Date: Wed May 19 23:12:28 2021 +0200
radv: Fix compatible image handle type for dmabufs.
Reviewed-by: Joshua Ashton <joshua at froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Fixes: 6c83e3ea98b7 ("radv: Add format modifier format queries.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10891>
(cherry picked from commit 36d0ff46822c9983ec60015f575820c4acc88017)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8ef35632d793931107bd163f18eac4b06b0a9d7
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon May 17 15:21:13 2021 +0200
aco: fix derivatives/intrinsics with SGPR sources
ds_swizzle_b32 requires a VGPR and DPP can't encode SGPR sources.
Fixes
dEQP-VK.graphicsfuzz.cov-derivative-uniform-vector-global-loop-count.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10840>
(cherry picked from commit fe2a5716ee7f99564690dc7eabbc5ada39d1d187)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0131939571870fa551741f3e4efccc120494b92
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 25 10:36:23 2020 -0800
nir/algebraic: Invert comparisons less often
This fixes the piglit test range_analysis_fsat_of_nan.shader_test. That
test contains some code like
o = saturate(X) > 0 ? vec4(1.0, 0.0, 0.0, 1.0)
: vec4(0.0, 1.0, 0.0, 1.0);
A clever optimizer will convert this to
o = vec4(float(saturate(X) > 0),
float(!(saturate(X) > 0)),
0, 1);
Due to the ordering of optimizations in the compiler, the `saturate`
operations are removed. This is safe even in the presense of NaN.
o = vec4(float(X > 0), float(!(X > 0)), 0, 1);
Since the calculations are not marked precise, an overzealous
optimizer may reduce this to
o = vec4(float(X > 0), float(X <= 0), 0, 1);
This will result in black being output. The GLSL spec gives quite a bit
of leeway with respect to NaN, but that seems too far. The shader
author asked for a result of red or green. A result of black is still
"undefined behavior," but it's also a little mean.
This also enables CSE to do its job better.
v2: Update A530 expected image checksum for minetest.trace.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4531
Fixes: 0dbda153aae ("nir/algebraic: Flag inexact optimizations")
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Tiger Lake
total instructions in shared programs: 21041563 -> 21041789 (<.01%)
instructions in affected programs: 992066 -> 992292 (0.02%)
helped: 526
HURT: 548
helped stats (abs) min: 1 max: 16 x̄: 2.48 x̃: 2
helped stats (rel) min: 0.04% max: 5.56% x̄: 0.74% x̃: 0.49%
HURT stats (abs) min: 1 max: 27 x̄: 2.80 x̃: 2
HURT stats (rel) min: 0.04% max: 4.55% x̄: 0.59% x̃: 0.38%
95% mean confidence interval for instructions value: -0.00 0.42
95% mean confidence interval for instructions %-change: -0.12% <.01%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 855885569 -> 856118189 (0.03%)
cycles in affected programs: 343637248 -> 343869868 (0.07%)
helped: 907
HURT: 541
helped stats (abs) min: 1 max: 7724 x̄: 206.45 x̃: 36
helped stats (rel) min: <.01% max: 29.97% x̄: 1.01% x̃: 0.37%
HURT stats (abs) min: 1 max: 14177 x̄: 776.09 x̃: 31
HURT stats (rel) min: <.01% max: 29.94% x̄: 1.24% x̃: 0.35%
95% mean confidence interval for cycles value: 84.30 237.00
95% mean confidence interval for cycles %-change: -0.32% -0.01%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
LOST: 3
GAINED: 5
Ice Lake
total instructions in shared programs: 20027107 -> 20025352 (<.01%)
instructions in affected programs: 1068856 -> 1067101 (-0.16%)
helped: 1153
HURT: 273
helped stats (abs) min: 1 max: 14 x̄: 1.83 x̃: 1
helped stats (rel) min: 0.03% max: 5.66% x̄: 0.61% x̃: 0.35%
HURT stats (abs) min: 1 max: 15 x̄: 1.29 x̃: 1
HURT stats (rel) min: 0.16% max: 1.30% x̄: 0.58% x̃: 0.60%
95% mean confidence interval for instructions value: -1.33 -1.13
95% mean confidence interval for instructions %-change: -0.43% -0.34%
Instructions are helped.
total cycles in shared programs: 979499227 -> 979448725 (<.01%)
cycles in affected programs: 344261539 -> 344211037 (-0.01%)
helped: 1079
HURT: 441
helped stats (abs) min: 1 max: 9384 x̄: 147.78 x̃: 48
helped stats (rel) min: <.01% max: 31.83% x̄: 0.90% x̃: 0.33%
HURT stats (abs) min: 1 max: 7220 x̄: 247.07 x̃: 32
HURT stats (rel) min: <.01% max: 31.30% x̄: 1.52% x̃: 0.53%
95% mean confidence interval for cycles value: -70.01 3.56
95% mean confidence interval for cycles %-change: -0.35% -0.05%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 10564 -> 10568 (0.04%)
spills in affected programs: 143 -> 147 (2.80%)
helped: 0
HURT: 1
total fills in shared programs: 11343 -> 11347 (0.04%)
fills in affected programs: 287 -> 291 (1.39%)
helped: 0
HURT: 1
LOST: 3
GAINED: 2
Skylake
total instructions in shared programs: 18192274 -> 18190128 (-0.01%)
instructions in affected programs: 1000188 -> 998042 (-0.21%)
helped: 1149
HURT: 55
helped stats (abs) min: 1 max: 14 x̄: 1.92 x̃: 1
helped stats (rel) min: 0.04% max: 6.67% x̄: 0.67% x̃: 0.42%
HURT stats (abs) min: 1 max: 2 x̄: 1.05 x̃: 1
HURT stats (rel) min: 0.16% max: 0.55% x̄: 0.27% x̃: 0.26%
95% mean confidence interval for instructions value: -1.87 -1.69
95% mean confidence interval for instructions %-change: -0.67% -0.58%
Instructions are helped.
total cycles in shared programs: 960856054 -> 960728040 (-0.01%)
cycles in affected programs: 340840968 -> 340712954 (-0.04%)
helped: 1079
HURT: 233
helped stats (abs) min: 1 max: 7640 x̄: 170.95 x̃: 46
helped stats (rel) min: <.01% max: 30.20% x̄: 0.96% x̃: 0.28%
HURT stats (abs) min: 1 max: 6864 x̄: 242.23 x̃: 26
HURT stats (rel) min: <.01% max: 34.64% x̄: 2.10% x̃: 0.22%
95% mean confidence interval for cycles value: -135.62 -59.53
95% mean confidence interval for cycles %-change: -0.59% -0.25%
Cycles are helped.
LOST: 15
GAINED: 1
Broadwell
total instructions in shared programs: 17855624 -> 17853580 (-0.01%)
instructions in affected programs: 1012209 -> 1010165 (-0.20%)
helped: 1105
HURT: 52
helped stats (abs) min: 1 max: 13 x̄: 1.90 x̃: 1
helped stats (rel) min: 0.03% max: 6.67% x̄: 0.67% x̃: 0.36%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.13% max: 0.52% x̄: 0.26% x̃: 0.25%
95% mean confidence interval for instructions value: -1.86 -1.67
95% mean confidence interval for instructions %-change: -0.68% -0.58%
Instructions are helped.
total cycles in shared programs: 1029905447 -> 1029840699 (<.01%)
cycles in affected programs: 347102680 -> 347037932 (-0.02%)
helped: 1007
HURT: 211
helped stats (abs) min: 1 max: 1360 x̄: 89.76 x̃: 48
helped stats (rel) min: <.01% max: 16.26% x̄: 0.69% x̃: 0.25%
HURT stats (abs) min: 1 max: 1297 x̄: 121.51 x̃: 20
HURT stats (rel) min: <.01% max: 31.31% x̄: 1.21% x̃: 0.20%
95% mean confidence interval for cycles value: -62.39 -43.92
95% mean confidence interval for cycles %-change: -0.47% -0.25%
Cycles are helped.
total spills in shared programs: 20335 -> 20333 (<.01%)
spills in affected programs: 19 -> 17 (-10.53%)
helped: 2
HURT: 0
total fills in shared programs: 25905 -> 25899 (-0.02%)
fills in affected programs: 23 -> 17 (-26.09%)
helped: 2
HURT: 0
LOST: 9
GAINED: 0
Haswell
total instructions in shared programs: 16418516 -> 16417293 (<.01%)
instructions in affected programs: 223785 -> 222562 (-0.55%)
helped: 590
HURT: 67
helped stats (abs) min: 1 max: 15 x̄: 2.19 x̃: 1
helped stats (rel) min: 0.03% max: 6.52% x̄: 0.87% x̃: 0.60%
HURT stats (abs) min: 1 max: 2 x̄: 1.04 x̃: 1
HURT stats (rel) min: 0.04% max: 1.85% x̄: 0.44% x̃: 0.25%
95% mean confidence interval for instructions value: -2.01 -1.71
95% mean confidence interval for instructions %-change: -0.80% -0.67%
Instructions are helped.
total cycles in shared programs: 1037179754 -> 1037084874 (<.01%)
cycles in affected programs: 352541071 -> 352446191 (-0.03%)
helped: 1093
HURT: 182
helped stats (abs) min: 1 max: 888 x̄: 111.03 x̃: 64
helped stats (rel) min: <.01% max: 27.30% x̄: 0.84% x̃: 0.20%
HURT stats (abs) min: 1 max: 6777 x̄: 145.49 x̃: 21
HURT stats (rel) min: <.01% max: 24.10% x̄: 1.99% x̃: 0.29%
95% mean confidence interval for cycles value: -88.10 -60.73
95% mean confidence interval for cycles %-change: -0.58% -0.29%
Cycles are helped.
total spills in shared programs: 17457 -> 17456 (<.01%)
spills in affected programs: 12 -> 11 (-8.33%)
helped: 1
HURT: 0
total fills in shared programs: 20387 -> 20385 (<.01%)
fills in affected programs: 15 -> 13 (-13.33%)
helped: 1
HURT: 0
LOST: 6
GAINED: 1
Ivy Bridge and earlier platforms had similar results. (Ivy Bridge shown)
total instructions in shared programs: 15515482 -> 15513998 (<.01%)
instructions in affected programs: 239739 -> 238255 (-0.62%)
helped: 573
HURT: 57
helped stats (abs) min: 1 max: 20 x̄: 2.73 x̃: 2
helped stats (rel) min: 0.03% max: 9.84% x̄: 0.94% x̃: 0.55%
HURT stats (abs) min: 1 max: 2 x̄: 1.39 x̃: 1
HURT stats (rel) min: 0.09% max: 1.85% x̄: 0.52% x̃: 0.35%
95% mean confidence interval for instructions value: -2.57 -2.14
95% mean confidence interval for instructions %-change: -0.89% -0.73%
Instructions are helped.
total cycles in shared programs: 584509880 -> 584463152 (<.01%)
cycles in affected programs: 11765280 -> 11718552 (-0.40%)
helped: 661
HURT: 152
helped stats (abs) min: 1 max: 3073 x̄: 101.99 x̃: 32
helped stats (rel) min: <.01% max: 34.38% x̄: 1.46% x̃: 0.50%
HURT stats (abs) min: 1 max: 6637 x̄: 136.10 x̃: 15
HURT stats (rel) min: <.01% max: 24.19% x̄: 1.75% x̃: 0.25%
95% mean confidence interval for cycles value: -82.79 -32.16
95% mean confidence interval for cycles %-change: -1.11% -0.61%
Cycles are helped.
LOST: 9
GAINED: 0
Tiger Lake
Instructions in all programs: 160905127 -> 160900949 (-0.0%)
SENDs in all programs: 6812418 -> 6812085 (-0.0%)
Loops in all programs: 38225 -> 38225 (+0.0%)
Cycles in all programs: 7431911114 -> 7433914697 (+0.0%)
Spills in all programs: 192582 -> 192582 (+0.0%)
Fills in all programs: 304539 -> 304537 (-0.0%)
Ice Lake
Instructions in all programs: 145296733 -> 145292370 (-0.0%)
SENDs in all programs: 6863818 -> 6863485 (-0.0%)
Loops in all programs: 38219 -> 38219 (+0.0%)
Cycles in all programs: 8798257570 -> 8800204360 (+0.0%)
Spills in all programs: 216880 -> 216880 (+0.0%)
Fills in all programs: 334250 -> 334248 (-0.0%)
Skylake
Instructions in all programs: 135891485 -> 135887357 (-0.0%)
SENDs in all programs: 6803031 -> 6802698 (-0.0%)
Loops in all programs: 38216 -> 38216 (+0.0%)
Cycles in all programs: 8442221881 -> 8444201959 (+0.0%)
Spills in all programs: 194839 -> 194839 (+0.0%)
Fills in all programs: 301116 -> 301114 (-0.0%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
(cherry picked from commit 4246c2869c3c5fe3b08e6b1a7996186d040dda4a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67a7f96ecbc4937a2f7bacd96ebee1a95c31494a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 5 10:38:52 2020 -0700
nir/algebraic: Remove some optimizations of comparisons with fsat
When most of these patterns were created, we believed, incorrectly, that
fsat(NaN) was NaN. We have since realized that fsat(NaN) is zero.
Originally, this changed the patterns to use is_a_number. This didn't
help any shaders, so it's easier to just drop the optimizations.
This commit crossed paths with 4c3ad4d0658 ("nir/algebraic: mark more
optimization with fsat(NaN) as inexact") and bc123c396a9
("nir/algebraic: mark some optimizations with fsat(NaN) as inexact").
Given that these don't impact very many shaders, it seems safer to just
remove them.
As discussed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8716, I tried
modifying these patterns to use !(b cmp a). Unfortunately, on Intel
GPUs, the results were much worse than just removing the patterns
altogether.
Some other related patterns will be addressed in later commits.
There are still a number of patterns that use the identity fsat(1-X) ==
1 - fsat(X). If X is NaN, the former is zero while the latter is 1.0.
I haven't evaluted these patterns yet. If changes are needed in these
patterns, it should be a separate commit anyway.
v2: Replace arrow `=>` with `->` in comments because the `=>` looks a
lot like `<=` comparison. Suggested by Rhys.
Fixes: 92b75c126bb ("nir/algebraic: Replace checks that a value is between (or not) [0, 1]")
Fixes: a7f0c57673d ("nir/algebraic: Eliminate useless fsat() on operand of comparison w/value in (0, 1)")
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
All Intel hardware had similar results. (Ice Lake shown)
total instructions in shared programs: 20029060 -> 20029670 (<.01%)
instructions in affected programs: 69236 -> 69846 (0.88%)
helped: 0
HURT: 263
HURT stats (abs) min: 1 max: 20 x̄: 2.32 x̃: 1
HURT stats (rel) min: 0.30% max: 11.11% x̄: 1.35% x̃: 0.98%
95% mean confidence interval for instructions value: 1.86 2.78
95% mean confidence interval for instructions %-change: 1.18% 1.52%
Instructions are HURT.
total cycles in shared programs: 979821278 -> 979834425 (<.01%)
cycles in affected programs: 1476848 -> 1489995 (0.89%)
helped: 49
HURT: 204
helped stats (abs) min: 1 max: 812 x̄: 102.31 x̃: 20
helped stats (rel) min: 0.01% max: 21.43% x̄: 2.23% x̃: 0.52%
HURT stats (abs) min: 2 max: 2600 x̄: 89.02 x̃: 16
HURT stats (rel) min: 0.04% max: 27.27% x̄: 1.49% x̃: 0.72%
95% mean confidence interval for cycles value: 13.18 90.75
95% mean confidence interval for cycles %-change: 0.29% 1.25%
Cycles are HURT.
No fossil-db changes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
(cherry picked from commit d69ba58644d1f34ca525f283a80f78fc371abc81)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=938fdfa0d93ba301e637915e2b046e1896f754bc
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Fri May 14 10:36:27 2021 -0400
panfrost: Fix pan_blend_to_fixed_function_equation prototype
Doesn't need the whole state, just the equation itself.
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Fixes: 93824b6451a ("panfrost: Move the blend logic out of the gallium driver")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10869>
(cherry picked from commit d7590efd2584881c3ea04198ff8b0ab0b54d9d92)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7541ba8945f27e926a04d0c8b30afad289d7527e
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Fri May 14 10:01:50 2021 -0400
panfrost: Fix blend constant fetch prototype
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Fixes: 93824b6451a ("panfrost: Move the blend logic out of the gallium driver")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10869>
(cherry picked from commit 5d3e2b5e9e1718ed414b6b73e2ff8b47b531ed6c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f60f062d80a8921523baba31f7849927b4deceaa
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Fri May 14 09:50:14 2021 -0400
panfrost: Fix is_opaque prototype
Fixes: 93824b6451a ("panfrost: Move the blend logic out of the gallium driver")
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10869>
(cherry picked from commit c35194b945cec0fb005d3f2ec417152f8acede5b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd3dc855078b2fa1c25a91165a4ca2e057eff721
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Fri May 14 09:47:37 2021 -0400
panfrost: Fix the reads_dest prototype
Takes too much state, only pass what we need.
Fixes: 93824b6451a ("panfrost: Move the blend logic out of the gallium driver")
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10869>
(cherry picked from commit a0592066b0c5408b6353c905d8f218c4cf54572a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe5b1ad32d08e08692fb0b92460dc4764abf805d
Author: Adam Jackson <ajax at redhat.com>
Date: Tue May 11 11:07:20 2021 -0400
zink/ntv: Don't call free() on ralloc'd memory
Caught this with an LTO build:
[1465/1465] Linking target src/gallium/targets/dri/libgallium_dri.so
In function ‘spirv_shader_delete’,
inlined from ‘nir_to_spirv’ at ../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c:3907:7:
../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c:3916:4: warning: ‘free’ called on pointer ‘block_1394’ with nonzero offset 48 [-Wfree-nonheap-object]
3916 | FREE(s);
| ^
../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c: In function ‘nir_to_spirv’:
../src/util/ralloc.c:133:18: note: returned from ‘malloc’
133 | void *block = malloc(align64(size + sizeof(ralloc_header),
| ^
Since s->words is allocated on the same ralloc context we can simplify
further by freeing the context all at once.
Reviewed-by: Emma Anholt <emma at anholt.net>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10754>
(cherry picked from commit 584145ea882b710027ce620a5d505bd25ab284b1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aba4478641747bf50cd28dda85d4135635c2c27e
Author: Eric Engestrom <eric at engestrom.ch>
Date: Tue May 25 10:15:45 2021 +0200
.pick_status.json: Update to 507e8907af913ab7b89211240568b8002b3475f1
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fadaaf31c26688206a982d3f8f7b60b10d1d0ddb
Author: Eric Engestrom <eric at engestrom.ch>
Date: Tue May 25 10:11:53 2021 +0200
.pick_status.json: Update to b663c544177e9547793ee405887f0d41c50e6d1d
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5eeedb6e9f6f3895d1825af5c2f6ef0e74b4cffd
Author: Eric Engestrom <eric at engestrom.ch>
Date: Tue May 25 10:06:38 2021 +0200
pick-ui & .pick_status.json: rename `master_sha` to `main_sha`
I should've done that instead of the change I did in
b125ee559a3d733c2584 ("bin/pick: Rename master branch to main").
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=acb53b268f79375220f0d723f152a69251f3126d
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Tue May 4 15:30:27 2021 -0500
intel/vec4: Don't spill fp64 registers more than once
The way we handle spilling for fp64 in vec4 is to emit a series of MOVs
which swizzles the data around and then a pair of 32-bit spills. This
works great except that the next time we go to pick a spill reg, the
compiler isn't smart enough to figure out that the register has already
been spilled. Normally we do this by looking at the sources of spill
instructions (or destinations of fills) but, because it's separated from
the actual value by a MOV, we can't see it. This commit adds a new
opcode VEC4_OPCODE_MOV_FOR_SCRATCH which is identical to MOV in
semantics except that it lets RA know not to spill again.
Fixes: 82c69426a5a3 "i965/vec4: support basic spilling of 64-bit registers"
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
(cherry picked from commit 2db88679432bd34a2c4ed761baec747192fa3e60)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=29c18f3c3bf8dc8e675a828cbb2db0396ce7ad1e
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Sun May 2 17:55:15 2021 -0500
anv: Support pushing shader constants
Usually, nir_opt_constant_folding will get rid of any load_constant
intrinsics which might possibly be pushed but there are rare cases where
we can still end up with them. Better to handle them.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
(cherry picked from commit c01354d5c4433452164e70a54e7bbfabf2443b50)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=49f846f596d4e5edfa6c59beb6aed3bfe8caa6e1
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Sun May 2 17:54:57 2021 -0500
anv: Plumb the shader into push constant helpers
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
(cherry picked from commit 24b3e71fa9038972292e10d236b8c27ec2fcef4f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=88bd86baa02257e054c93888d8caa9084e50b84d
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Mon May 17 14:37:54 2021 +0100
aco: disallow SGPRs on DPP instructions
They can't be encoded.
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10841>
(cherry picked from commit 3013670dfda17565e689f402c5fc14806b3361ae)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d357aa784194abfbf5b0b847463cd29c733cc78
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri May 14 16:25:32 2021 +0100
draw: Allocate extra padding for extra shader outputs.
This prevents read buffer overflows in dup_vertex(), when draw stages
allocate extra shader outputs after the vertex buffers are allocated.
The original issue can be exercised with upcoming
piglit/tests/general/vertex-fallbacks.c test.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Cc: 21.0 21.1 <mesa-stable at lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10836>
(cherry picked from commit 250605c57d8eb01c818cf639e412ca2f7cf4b00a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9163f9dd017cbad379c75209be2800b750861b8
Author: Eric Engestrom <eric at engestrom.ch>
Date: Wed May 19 22:25:17 2021 +0200
.pick_status.json: Update to 17861aff9614abfea3b8a8f111a114b26b351915
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