Mesa (staging/21.3): radv: Disable coherent L2 optimization on cards with noncoherent L2.

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Module: Mesa
Branch: staging/21.3
Commit: 93c9bb607aa72786810240a1b82100bcd41ddd51
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=93c9bb607aa72786810240a1b82100bcd41ddd51

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Mon Nov  1 16:39:50 2021 +0100

radv: Disable coherent L2 optimization on cards with noncoherent L2.

With high likelihood we are forgetting to set the noncoherent bits
somewhere but I don't have the HW to debug. To avoid user pain
disable this optimization on these GPUs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5505
Fixes: fd8210f27ed ("radv: Try to do a better job of dealing with L2 coherent images.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13620>
(cherry picked from commit d66514aacccec28fa66afd58bc19580008e8078e)

---

 .pick_status.json                |  2 +-
 src/amd/vulkan/radv_cmd_buffer.c | 15 +++++++++++----
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index c702754acca..1e7582d2185 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -184,7 +184,7 @@
         "description": "radv: Disable coherent L2 optimization on cards with noncoherent L2.",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "fd8210f27ede11583e3a5d55066cb61d9988357b"
     },
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 2c236b2bdd2..dd2ed5078fa 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3740,6 +3740,14 @@ radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags src_st
    }
 }
 
+static bool
+can_skip_buffer_l2_flushes(struct radv_device *device)
+{
+   return device->physical_device->rad_info.chip_class == GFX9 ||
+          (device->physical_device->rad_info.chip_class >= GFX10 &&
+           !device->physical_device->rad_info.tcc_rb_non_coherent);
+}
+
 /*
  * In vulkan barriers have two kinds of operations:
  *
@@ -3871,8 +3879,8 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags dst_flag
 
    /* All the L2 invalidations below are not the CB/DB. So if there are no incoherent images
     * in the L2 cache in CB/DB mode then they are already usable from all the other L2 clients. */
-   image_is_coherent |= cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
-                        !cmd_buffer->state.rb_noncoherent_dirty;
+   image_is_coherent |=
+      can_skip_buffer_l2_flushes(cmd_buffer->device) && !cmd_buffer->state.rb_noncoherent_dirty;
 
    u_foreach_bit(b, dst_flags)
    {
@@ -4763,8 +4771,7 @@ radv_EndCommandBuffer(VkCommandBuffer commandBuffer)
       /* Flush noncoherent images on GFX9+ so we can assume they're clean on the start of a
        * command buffer.
        */
-      if (cmd_buffer->state.rb_noncoherent_dirty &&
-          cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
+      if (cmd_buffer->state.rb_noncoherent_dirty && can_skip_buffer_l2_flushes(cmd_buffer->device))
          cmd_buffer->state.flush_bits |= radv_src_access_flush(
             cmd_buffer,
             VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,