Mesa (staging/21.3): tu: fix rast state allocation size on a6xx gen4

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Wed Nov 3 20:07:53 UTC 2021


Module: Mesa
Branch: staging/21.3
Commit: 6939483a92312b118fb8c1c40cf5001ca0a34bce
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6939483a92312b118fb8c1c40cf5001ca0a34bce

Author: Danylo Piliaiev <dpiliaiev at igalia.com>
Date:   Wed Nov  3 14:05:23 2021 +0200

tu: fix rast state allocation size on a6xx gen4

A few regs were added without changing the size of draw state.

Fixes: 4e05338d99abbf2858a0d8444ffc53028fe23051 ("turnip: Rast updates for a6xx gen4")

Signed-off-by: Danylo Piliaiev <dpiliaiev at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13644>
(cherry picked from commit 79fcd63bd60ac46249c6dfcfa0eeef296ea3d04a)

---

 .pick_status.json                  | 2 +-
 src/freedreno/vulkan/tu_pipeline.c | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index c48453e5af7..d05e47a0147 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -130,7 +130,7 @@
         "description": "tu: fix rast state allocation size on a6xx gen4",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "4e05338d99abbf2858a0d8444ffc53028fe23051"
     },
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 7543e4503c0..a4a9f9202ee 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -2776,7 +2776,9 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
    }
 
    struct tu_cs cs;
-   uint32_t cs_size = 9 + (builder->emit_msaa_state ? 11 : 0);
+   uint32_t cs_size = 9 +
+      (builder->device->physical_device->info->a6xx.has_shading_rate ? 8 : 0) +
+      (builder->emit_msaa_state ? 11 : 0);
    pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, cs_size);
 
    tu_cs_emit_regs(&cs,



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