Mesa (main): ac/surface: use a less strict condition in is_dcc_supported_by_L2
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Thu Nov 4 09:04:40 UTC 2021
Module: Mesa
Branch: main
Commit: 84d4bda8e5cb4d844d3892fcc317412104d8f2bc
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=84d4bda8e5cb4d844d3892fcc317412104d8f2bc
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Wed Oct 27 14:51:23 2021 +0200
ac/surface: use a less strict condition in is_dcc_supported_by_L2
While Mesa chooses to always use independent_128B_blocks, other drivers
can make different choices.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13550>
---
src/amd/common/ac_surface.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 121093979b3..d39c71318ee 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1453,23 +1453,24 @@ ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info,
surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
}
+ bool valid_64b = surf->u.gfx9.color.dcc.independent_64B_blocks &&
+ surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B;
+ bool valid_128b = surf->u.gfx9.color.dcc.independent_128B_blocks &&
+ surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B;
+
if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14) {
/* Either 64B or 128B can be used, but not both.
* If 64B is used, DCC image stores are unsupported.
*/
return surf->u.gfx9.color.dcc.independent_64B_blocks != surf->u.gfx9.color.dcc.independent_128B_blocks &&
- (!surf->u.gfx9.color.dcc.independent_64B_blocks ||
- surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) &&
- (!surf->u.gfx9.color.dcc.independent_128B_blocks ||
- surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B);
+ (valid_64b || valid_128b);
}
- /* 128B is recommended, but 64B can be set too if needed for 4K by DCN.
- * Since there is no reason to ever disable 128B, require it.
- * If 64B is used, DCC image stores are unsupported.
- */
- return surf->u.gfx9.color.dcc.independent_128B_blocks &&
- surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
+ /* Valid settings are the same as NAVI14 + (64B && 128B && max_compressed_block_size == 64B) */
+ return (surf->u.gfx9.color.dcc.independent_64B_blocks != surf->u.gfx9.color.dcc.independent_128B_blocks &&
+ (valid_64b || valid_128b)) ||
+ (surf->u.gfx9.color.dcc.independent_64B_blocks &&
+ surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
}
static bool gfx10_DCN_requires_independent_64B_blocks(const struct radeon_info *info,
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