Mesa (main): intel/dev: fix HSW GT3 number of subslices in slice1

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Module: Mesa
Branch: main
Commit: d1db5d562af6cd9447bb564797d67dd27ff95024
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1db5d562af6cd9447bb564797d67dd27ff95024

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Sat Apr  3 13:22:50 2021 +0300

intel/dev: fix HSW GT3 number of subslices in slice1

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10015>

---

 src/intel/dev/intel_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c
index 70ff3703a02..3c72be03ca8 100644
--- a/src/intel/dev/intel_device_info.c
+++ b/src/intel/dev/intel_device_info.c
@@ -373,7 +373,7 @@ static const struct intel_device_info intel_device_info_hsw_gt2 = {
 static const struct intel_device_info intel_device_info_hsw_gt3 = {
    HSW_FEATURES, .gt = 3,
    .num_slices = 2,
-   .num_subslices = { 2, },
+   .num_subslices = { 2, 2, },
    .num_eu_per_subslice = 10,
    .num_thread_per_eu = 7,
    .l3_banks = 8,