Mesa (main): freedreno/a4xx: add proper buffer texture support

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Module: Mesa
Branch: main
Commit: 6566eae93333b8cc4d96f85522788e18c5cafa90
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6566eae93333b8cc4d96f85522788e18c5cafa90

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sat Nov 13 23:51:54 2021 -0500

freedreno/a4xx: add proper buffer texture support

Rather than faking it as a 1d texture, add the buffer texture type, and
allow a full range of sizes.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13805>

---

 src/freedreno/registers/adreno/a4xx.xml          |  4 +++-
 src/gallium/drivers/freedreno/a4xx/fd4_emit.c    | 13 ++++++++++---
 src/gallium/drivers/freedreno/a4xx/fd4_texture.c |  6 ++++--
 src/gallium/drivers/freedreno/freedreno_screen.c |  8 ++------
 4 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/src/freedreno/registers/adreno/a4xx.xml b/src/freedreno/registers/adreno/a4xx.xml
index f98ac60b70e..68ed784fc34 100644
--- a/src/freedreno/registers/adreno/a4xx.xml
+++ b/src/freedreno/registers/adreno/a4xx.xml
@@ -2326,6 +2326,7 @@ perhaps they should be taken with a grain of salt
 		<value name="A4XX_TEX_2D" value="1"/>
 		<value name="A4XX_TEX_CUBE" value="2"/>
 		<value name="A4XX_TEX_3D" value="3"/>
+		<value name="A4XX_TEX_BUFFER" value="4"/>
 	</enum>
 	<reg32 offset="0" name="0">
 		<bitfield name="TILED" pos="0" type="boolean"/>
@@ -2336,7 +2337,7 @@ perhaps they should be taken with a grain of salt
 		<bitfield name="SWIZ_W" low="13" high="15" type="a4xx_tex_swiz"/>
 		<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
 		<bitfield name="FMT" low="22" high="28" type="a4xx_tex_fmt"/>
-		<bitfield name="TYPE" low="29" high="30" type="a4xx_tex_type"/>
+		<bitfield name="TYPE" low="29" high="31" type="a4xx_tex_type"/>
 	</reg32>
 	<reg32 offset="1" name="1">
 		<bitfield name="HEIGHT" low="0" high="14" type="uint"/>
@@ -2345,6 +2346,7 @@ perhaps they should be taken with a grain of salt
 	<reg32 offset="2" name="2">
 		<!-- minimum pitch (for mipmap levels): log2(pitchalign / 32) -->
 		<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
+		<bitfield name="BUFFER" pos="6" type="boolean"/>
 		<doc>Pitch in bytes (so actually stride)</doc>
 		<bitfield name="PITCH" low="9" high="29" type="uint"/>
 		<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 9b6c667016b..8bfeb1877bc 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -148,14 +148,21 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
    bool needs_border = false;
    unsigned i;
 
-   if (tex->num_samplers > 0) {
-      int num_samplers;
+   if (tex->num_samplers > 0 || tex->num_textures > 0) {
+      int num_samplers = tex->num_samplers;
+
+      /* We want to always make sure that there's at least one sampler if
+       * there are going to be texture accesses. Gallium might not upload a
+       * sampler for e.g. buffer textures.
+       */
+      if (num_samplers == 0)
+         num_samplers++;
 
       /* not sure if this is an a420.0 workaround, but we seem
        * to need to emit these in pairs.. emit a final dummy
        * entry if odd # of samplers:
        */
-      num_samplers = align(tex->num_samplers, 2);
+      num_samplers = align(num_samplers, 2);
 
       /* output sampler state: */
       OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * num_samplers));
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
index 5c7b94c472a..eb26f7d2c1f 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
@@ -132,6 +132,7 @@ tex_type(unsigned target)
    default:
       assert(0);
    case PIPE_BUFFER:
+      return A4XX_TEX_BUFFER;
    case PIPE_TEXTURE_1D:
    case PIPE_TEXTURE_1D_ARRAY:
       return A4XX_TEX_1D;
@@ -193,8 +194,9 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 
       lvl = 0;
       so->texconst1 =
-         A4XX_TEX_CONST_1_WIDTH(elements) | A4XX_TEX_CONST_1_HEIGHT(1);
-      so->texconst2 = A4XX_TEX_CONST_2_PITCH(elements * rsc->layout.cpp);
+         A4XX_TEX_CONST_1_WIDTH(elements & MASK(15)) |
+         A4XX_TEX_CONST_1_HEIGHT(elements >> 15);
+      so->texconst2 = A4XX_TEX_CONST_2_BUFFER;
       so->offset = cso->u.buf.offset;
    } else {
       unsigned miplevels;
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index e7005658112..e2b963b8fe1 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -285,9 +285,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
       if (is_a3xx(screen))
          return 16;
-      if (is_a4xx(screen))
-         return 32;
-      if (is_a5xx(screen) || is_a6xx(screen))
+      if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
          return 64;
       return 0;
    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
@@ -296,14 +294,12 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        */
       if (is_a3xx(screen))
          return 8192;
-      if (is_a4xx(screen))
-         return 16384;
 
       /* Note that the Vulkan blob on a540 and 640 report a
        * maxTexelBufferElements of just 65536 (the GLES3.2 and Vulkan
        * minimum).
        */
-      if (is_a5xx(screen) || is_a6xx(screen))
+      if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
          return 1 << 27;
       return 0;