Mesa (main): freedreno/a4xx: indicate whether outputs are uint/sint

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Module: Mesa
Branch: main
Commit: 45606b51cc9fb1da27242b81e23d3430fec3fcd4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=45606b51cc9fb1da27242b81e23d3430fec3fcd4

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Mon Nov 15 01:23:01 2021 -0500

freedreno/a4xx: indicate whether outputs are uint/sint

Unclear whether this fixes anything, but the blob does seem to set
these. (Discovered while trying to determine if value clamping was
missing for non-32-bit integer formats, which fail in some tests.)

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13806>

---

 src/freedreno/registers/adreno/a4xx.xml          |  2 ++
 src/gallium/drivers/freedreno/a4xx/fd4_program.c | 12 ++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/freedreno/registers/adreno/a4xx.xml b/src/freedreno/registers/adreno/a4xx.xml
index 68ed784fc34..498e86614d2 100644
--- a/src/freedreno/registers/adreno/a4xx.xml
+++ b/src/freedreno/registers/adreno/a4xx.xml
@@ -1666,6 +1666,8 @@ perhaps they should be taken with a grain of salt
 		<reg32 offset="0x0" name="REG">
 			<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
 			<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
+			<bitfield name="COLOR_SINT" pos="10" type="boolean"/>
+			<bitfield name="COLOR_UINT" pos="11" type="boolean"/>
 			<bitfield name="MRTFORMAT" low="12" high="17" type="a4xx_color_fmt"/>
 			<bitfield name="COLOR_SRGB" pos="18" type="boolean"/>
 		</reg32>
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_program.c b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
index bfee65211ea..2a8161c8860 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_program.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
@@ -436,14 +436,22 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit, int nr,
    for (i = 0; i < 8; i++) {
       enum a4xx_color_fmt format = 0;
       bool srgb = false;
+      bool uint = false;
+      bool sint = false;
       if (i < nr) {
          format = fd4_emit_format(bufs[i]);
-         if (bufs[i] && !emit->no_decode_srgb)
-            srgb = util_format_is_srgb(bufs[i]->format);
+         if (bufs[i]) {
+            if (!emit->no_decode_srgb)
+               srgb = util_format_is_srgb(bufs[i]->format);
+            uint = util_format_is_pure_uint(bufs[i]->format);
+            sint = util_format_is_pure_sint(bufs[i]->format);
+         }
       }
       OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
                         A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
                         COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
+                        COND(uint, A4XX_SP_FS_MRT_REG_COLOR_UINT) |
+                        COND(sint, A4XX_SP_FS_MRT_REG_COLOR_SINT) |
                         COND(color_regid[i] & HALF_REG_ID,
                              A4XX_SP_FS_MRT_REG_HALF_PRECISION));
    }