Mesa (staging/21.3): intel/genxml: Fix MI_FLUSH_DW to actually specify the length properly

[GitLab Mirror]

Module: Mesa
Branch: staging/21.3
Commit: e7b428a98a201b008ed5491a9229df8573901fe4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7b428a98a201b008ed5491a9229df8573901fe4

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Nov  9 18:34:29 2021 -0800

intel/genxml: Fix MI_FLUSH_DW to actually specify the length properly

Fixes: 569afd37f15 ("intel/genxml: Copy gen12.xml to gen125.xml")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809>
(cherry picked from commit 29025f66fd3fa009cc79f844449ebc05d252804a)

---

 .pick_status.json           | 2 +-
 src/intel/genxml/gen11.xml  | 2 +-
 src/intel/genxml/gen125.xml | 2 +-
 src/intel/genxml/gen6.xml   | 2 +-
 src/intel/genxml/gen7.xml   | 2 +-
 src/intel/genxml/gen75.xml  | 2 +-
 src/intel/genxml/gen8.xml   | 2 +-
 src/intel/genxml/gen9.xml   | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 2d41ee01518..73ed6ccb1d7 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -382,7 +382,7 @@
         "description": "intel/genxml: Fix MI_FLUSH_DW to actually specify the length properly",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "569afd37f15cfc51750a71fd695f4496b0358fbb"
     },
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index ca66b8a35fc..1bc72aa6d8d 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -5918,7 +5918,7 @@
   </instruction>
 
   <instruction name="MI_FLUSH_DW" bias="2" length="5" engine="video">
-    <field name="DWord Length" start="0" end="5" type="uint"/>
+    <field name="DWord Length" start="0" end="5" type="uint" default="3"/>
     <field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
     <field name="Notify Enable" start="8" end="8" type="bool"/>
     <field name="Flush LLC" start="9" end="9" type="bool"/>
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index dac592d0b69..cf8b1360147 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -6010,7 +6010,7 @@
   </instruction>
 
   <instruction name="MI_FLUSH_DW" bias="2" length="5" engine="video">
-    <field name="DWord Length" start="0" end="5" type="uint"/>
+    <field name="DWord Length" start="0" end="5" type="uint" default="3"/>
     <field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
     <field name="Notify Enable" start="8" end="8" type="bool"/>
     <field name="Flush LLC" start="9" end="9" type="bool"/>
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 041365dbfa6..386684338d1 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -2486,7 +2486,7 @@
   </instruction>
 
   <instruction name="MI_FLUSH_DW" bias="2" length="4" engine="video">
-    <field name="DWord Length" start="0" end="5" type="uint"/>
+    <field name="DWord Length" start="0" end="5" type="uint" default="2"/>
     <field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
     <field name="Notify Enable" start="8" end="8" type="bool"/>
     <field name="Post-Sync Operation" start="14" end="15" type="uint"/>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index d7367382342..f636844887b 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -3336,7 +3336,7 @@
   </instruction>
 
   <instruction name="MI_FLUSH_DW" bias="2" length="4" engine="video">
-    <field name="DWord Length" start="0" end="5" type="uint"/>
+    <field name="DWord Length" start="0" end="5" type="uint" default="2"/>
     <field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
     <field name="Notify Enable" start="8" end="8" type="bool"/>
     <field name="Post-Sync Operation" start="14" end="15" type="uint"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 1f29e2e24ec..3b634ac4969 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -3638,7 +3638,7 @@
   </instruction>
 
   <instruction name="MI_FLUSH_DW" bias="2" length="4" engine="video">
-    <field name="DWord Length" start="0" end="5" type="uint"/>
+    <field name="DWord Length" start="0" end="5" type="uint" default="2"/>
     <field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
     <field name="Notify Enable" start="8" end="8" type="bool"/>
     <field name="Post-Sync Operation" start="14" end="15" type="uint"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 0447efc7d8e..e4ae342199a 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -4152,7 +4152,7 @@
   </instruction>
 
   <instruction name="MI_FLUSH_DW" bias="2" length="5" engine="video">
-    <field name="DWord Length" start="0" end="5" type="uint"/>
+    <field name="DWord Length" start="0" end="5" type="uint" default="3"/>
     <field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
     <field name="Notify Enable" start="8" end="8" type="bool"/>
     <field name="Post-Sync Operation" start="14" end="15" type="uint"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index bbce560a63e..b9589f6f7c5 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -5536,7 +5536,7 @@
   </instruction>
 
   <instruction name="MI_FLUSH_DW" bias="2" length="5" engine="video">
-    <field name="DWord Length" start="0" end="5" type="uint"/>
+    <field name="DWord Length" start="0" end="5" type="uint" default="3"/>
     <field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
     <field name="Notify Enable" start="8" end="8" type="bool"/>
     <field name="Flush LLC" start="9" end="9" type="bool"/>