Mesa (main): freedreno/a5xx: Document the sRGB bit on RB_2D_SRC/DST info.

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Module: Mesa
Branch: main
Commit: 5071d39cb27ea76f41ba23003976d3ea14f6a0b9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5071d39cb27ea76f41ba23003976d3ea14f6a0b9

Author: Emma Anholt <emma at anholt.net>
Date:   Wed Nov 17 16:27:16 2021 -0800

freedreno/a5xx: Document the sRGB bit on RB_2D_SRC/DST info.

Noticed while looking through my set of traces for where the average bit
might be.  Same spot as on a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13867>

---

 src/freedreno/registers/adreno/a5xx.xml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/freedreno/registers/adreno/a5xx.xml b/src/freedreno/registers/adreno/a5xx.xml
index 5313f7bc0fd..536fcafc94e 100644
--- a/src/freedreno/registers/adreno/a5xx.xml
+++ b/src/freedreno/registers/adreno/a5xx.xml
@@ -2767,6 +2767,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
 		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
 		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
 		<bitfield name="FLAGS" pos="12" type="boolean"/>
+		<bitfield name="SRGB" pos="13" type="boolean"/>
 	</bitset>
 
 	<reg32 offset="0x2107" name="RB_2D_SRC_INFO" type="a5xx_2d_surf_info"/>