Mesa (main): intel: move timestamp scaling helper to intel/perf
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Mon Nov 22 12:17:08 UTC 2021
Module: Mesa
Branch: main
Commit: 5a2cff9bc8bb8a0db2ef4fb97f31f93b2ad5c796
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a2cff9bc8bb8a0db2ef4fb97f31f93b2ad5c796
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Nov 18 13:37:18 2021 +0200
intel: move timestamp scaling helper to intel/perf
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
---
src/intel/ds/intel_pps_driver.cc | 21 ++++++---------------
src/intel/perf/intel_perf.c | 11 +++++++++++
src/intel/perf/intel_perf.h | 5 +++++
3 files changed, 22 insertions(+), 15 deletions(-)
diff --git a/src/intel/ds/intel_pps_driver.cc b/src/intel/ds/intel_pps_driver.cc
index 97729aa7ebc..8a9788b7a6b 100644
--- a/src/intel/ds/intel_pps_driver.cc
+++ b/src/intel/ds/intel_pps_driver.cc
@@ -40,16 +40,6 @@ uint64_t IntelDriver::get_min_sampling_period_ns()
return (2.f * perf->devinfo.timestamp_frequency) / 1000000000ull;
}
-uint64_t scale_gpu_timestamp(uint64_t ts, uint64_t timestamp_frequency)
-{
- // Try to avoid going over the 64bits when doing the scaling
- uint64_t lower_ts = ts >> 6;
- uint64_t scaled_ts = lower_ts * 1000000000ull / timestamp_frequency;
- scaled_ts <<= 6;
- scaled_ts += (ts & 0x3f) * 1000000000ull / timestamp_frequency;
- return scaled_ts;
-}
-
uint64_t read_gpu_timestamp(int drm_fd)
{
drm_i915_reg_read reg_read = {};
@@ -233,8 +223,8 @@ std::vector<PerfRecord> IntelDriver::parse_perf_records(const std::vector<uint8_
uint64_t gpu_timestamp = gpu_timestamp_udw + gpu_timestamp_ldw;
- auto duration = scale_gpu_timestamp(gpu_timestamp - prev_gpu_timestamp,
- perf->devinfo.timestamp_frequency);
+ auto duration = intel_perf_scale_gpu_timestamp(&perf->devinfo,
+ gpu_timestamp - prev_gpu_timestamp);
// Skip perf-records that are too short by checking
// the distance between last report and this one
@@ -328,7 +318,8 @@ uint64_t IntelDriver::gpu_next()
// Consume first record
records.erase(std::begin(records), std::begin(records) + 1);
- return scale_gpu_timestamp(gpu_timestamp, perf->devinfo.timestamp_frequency);
+ return intel_perf_scale_gpu_timestamp(&perf->devinfo,
+ gpu_timestamp);
}
uint64_t IntelDriver::next()
@@ -345,8 +336,8 @@ uint32_t IntelDriver::gpu_clock_id() const
uint64_t IntelDriver::gpu_timestamp() const
{
- return scale_gpu_timestamp(read_gpu_timestamp(drm_device.fd),
- perf->devinfo.timestamp_frequency);
+ return intel_perf_scale_gpu_timestamp(&perf->devinfo,
+ read_gpu_timestamp(drm_device.fd));
}
} // namespace pps
diff --git a/src/intel/perf/intel_perf.c b/src/intel/perf/intel_perf.c
index f750e673fd3..b96e187c8bd 100644
--- a/src/intel/perf/intel_perf.c
+++ b/src/intel/perf/intel_perf.c
@@ -1027,6 +1027,17 @@ can_use_mi_rpc_bc_counters(const struct intel_device_info *devinfo)
return devinfo->ver <= 11;
}
+uint64_t intel_perf_scale_gpu_timestamp(const struct intel_device_info *devinfo,
+ uint64_t ts)
+{
+ // Try to avoid going over the 64bits when doing the scaling
+ uint64_t lower_ts = ts >> 6;
+ uint64_t scaled_ts = lower_ts * 1000000000ull / devinfo->timestamp_frequency;
+ scaled_ts <<= 6;
+ scaled_ts += (ts & 0x3f) * 1000000000ull / devinfo->timestamp_frequency;
+ return scaled_ts;
+}
+
uint64_t
intel_perf_report_timestamp(const struct intel_perf_query_info *query,
const uint32_t *report)
diff --git a/src/intel/perf/intel_perf.h b/src/intel/perf/intel_perf.h
index 83bd15c2611..8894a29b9c2 100644
--- a/src/intel/perf/intel_perf.h
+++ b/src/intel/perf/intel_perf.h
@@ -464,6 +464,11 @@ void intel_perf_query_result_accumulate(struct intel_perf_query_result *result,
uint64_t intel_perf_report_timestamp(const struct intel_perf_query_info *query,
const uint32_t *report);
+/** Turn a GPU timestamp into a nanosecond value.
+ */
+uint64_t intel_perf_scale_gpu_timestamp(const struct intel_device_info *devinfo,
+ uint64_t ts);
+
/** Accumulate the delta between 2 snapshots of OA perf registers (layout
* should match description specified through intel_perf_query_register_layout).
*/
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