Mesa (main): intel/fs: Define and set correct sampler simd mode
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Tue Nov 23 07:08:05 UTC 2021
Module: Mesa
Branch: main
Commit: 2fa68cb7da525bcd17840fc23ff2cd542547118a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fa68cb7da525bcd17840fc23ff2cd542547118a
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date: Mon Jul 13 18:32:14 2020 -0700
intel/fs: Define and set correct sampler simd mode
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
---
src/intel/compiler/brw_eu_defines.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 68225ff91dd..4baa46c5fd4 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -1354,6 +1354,9 @@ enum brw_message_target {
#define BRW_SAMPLER_SIMD_MODE_SIMD16 2
#define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
+#define GFX10_SAMPLER_SIMD_MODE_SIMD8H 5
+#define GFX10_SAMPLER_SIMD_MODE_SIMD16H 6
+
/* GFX9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
* behavior by setting bit 22 of dword 2 in the message header. */
#define GFX9_SAMPLER_SIMD_MODE_SIMD8D 0
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