Mesa (staging/21.2): ir3/lower_pcopy: Fix shr.b illegal copy lowering

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Module: Mesa
Branch: staging/21.2
Commit: c2c06d38812c45f821f2a2136389706294201c15
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2c06d38812c45f821f2a2136389706294201c15

Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Tue Nov 16 15:32:58 2021 +0100

ir3/lower_pcopy: Fix shr.b illegal copy lowering

The immediate shouldn't be half-reg because the other source isn't.
Fixes an assertion failure with
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.35.

Fixes: 0ffcb19b9d9 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13818>
(cherry picked from commit 65da866ad96bbe5a1683c98191331827ea3bd580)

---

 .pick_status.json                          | 2 +-
 src/freedreno/ir3/ir3_lower_parallelcopy.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 5774cb8b6d5..27330018652 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1102,7 +1102,7 @@
         "description": "ir3/lower_pcopy: Fix shr.b illegal copy lowering",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "0ffcb19b9d9fbe902224542047c389a661fbf816"
     },
diff --git a/src/freedreno/ir3/ir3_lower_parallelcopy.c b/src/freedreno/ir3/ir3_lower_parallelcopy.c
index 8807dd2d157..80a841662a4 100644
--- a/src/freedreno/ir3/ir3_lower_parallelcopy.c
+++ b/src/freedreno/ir3/ir3_lower_parallelcopy.c
@@ -223,12 +223,12 @@ do_copy(struct ir3_compiler *compiler, struct ir3_instruction *instr,
             cov->cat1.src_type = TYPE_U32;
             ir3_instr_move_before(cov, instr);
          } else {
-            /* shr.b dst, src, h(16) */
+            /* shr.b dst, src, (16) */
             struct ir3_instruction *shr =
                ir3_instr_create(instr->block, OPC_SHR_B, 1, 2);
             ir3_dst_create(shr, dst_num, entry->flags);
             ir3_src_create(shr, src_num, entry->flags & ~IR3_REG_HALF);
-            ir3_src_create(shr, 0, entry->flags | IR3_REG_IMMED)->uim_val = 16;
+            ir3_src_create(shr, 0, IR3_REG_IMMED)->uim_val = 16;
             ir3_instr_move_before(shr, instr);
          }
          return;