Mesa (staging/21.2): aco/spill: use spills_entry instead of spills_exit to kill linear VGPRs

[GitLab Mirror]

Module: Mesa
Branch: staging/21.2
Commit: 07b3b6b4c410442af5be5fdee619e0b2e51da43b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=07b3b6b4c410442af5be5fdee619e0b2e51da43b

Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Tue Nov 16 17:33:11 2021 +0000

aco/spill: use spills_entry instead of spills_exit to kill linear VGPRs

If a predecessor has only spilled constants (no temporaries), spills_exit
will be empty.

fossil-db (Sienna Cichlid):
Totals from 2 (0.00% of 128647) affected shaders:
Latency: 139106 -> 139104 (-0.00%)

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5633
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13821>
(cherry picked from commit cc2894345f1161fcbb2f9b9150257e0f6b0b303e)

---

 .pick_status.json              | 2 +-
 src/amd/compiler/aco_spill.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index acacae06e5c..901f8ec535d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -553,7 +553,7 @@
         "description": "aco/spill: use spills_entry instead of spills_exit to kill linear VGPRs",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp
index 205a687b7e4..821ef85806c 100644
--- a/src/amd/compiler/aco_spill.cpp
+++ b/src/amd/compiler/aco_spill.cpp
@@ -1563,7 +1563,7 @@ assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr)
                continue;
 
             bool can_destroy = true;
-            for (std::pair<Temp, uint32_t> pair : ctx.spills_exit[block.linear_preds[0]]) {
+            for (std::pair<Temp, uint32_t> pair : ctx.spills_entry[block.index]) {
 
                if (ctx.interferences[pair.second].first.type() == RegType::sgpr &&
                    slots[pair.second] / ctx.wave_size == i) {