Mesa (main): radv: add support for VkMemoryBarrier2KHR

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Module: Mesa
Branch: main
Commit: e99c66ad196b46c4ea13c153dfd8f6f9cb701a76
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e99c66ad196b46c4ea13c153dfd8f6f9cb701a76

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Oct 12 17:54:41 2021 +0200

radv: add support for VkMemoryBarrier2KHR

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13549>

---

 src/amd/vulkan/radv_pass.c | 30 ++++++++++++++++++++++--------
 1 file changed, 22 insertions(+), 8 deletions(-)

diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
index 4935600b27f..591eb35b8bc 100644
--- a/src/amd/vulkan/radv_pass.c
+++ b/src/amd/vulkan/radv_pass.c
@@ -45,16 +45,30 @@ radv_render_pass_add_subpass_dep(struct radv_render_pass *pass, const VkSubpassD
    if (src == VK_SUBPASS_EXTERNAL)
       dst = 0;
 
+
+   /* From the Vulkan 1.2.195 spec:
+    *
+    * "If an instance of VkMemoryBarrier2 is included in the pNext chain, srcStageMask,
+    *  dstStageMask, srcAccessMask, and dstAccessMask parameters are ignored. The synchronization
+    *  and access scopes instead are defined by the parameters of VkMemoryBarrier2."
+    */
+   const VkMemoryBarrier2KHR *barrier =
+      vk_find_struct_const(dep->pNext, MEMORY_BARRIER_2_KHR);
+   VkPipelineStageFlags2KHR src_stage_mask = barrier ? barrier->srcStageMask : dep->srcStageMask;
+   VkAccessFlags2KHR src_access_mask = barrier ? barrier->srcAccessMask : dep->srcAccessMask;
+   VkPipelineStageFlags2KHR dst_stage_mask = barrier ? barrier->dstStageMask : dep->dstStageMask;
+   VkAccessFlags2KHR dst_access_mask = barrier ? barrier->dstAccessMask : dep->dstAccessMask;
+
    if (dst == VK_SUBPASS_EXTERNAL) {
-      if (dep->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
-         pass->end_barrier.src_stage_mask |= dep->srcStageMask;
-      pass->end_barrier.src_access_mask |= dep->srcAccessMask;
-      pass->end_barrier.dst_access_mask |= dep->dstAccessMask;
+      if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR)
+         pass->end_barrier.src_stage_mask |= src_stage_mask;
+      pass->end_barrier.src_access_mask |= src_access_mask;
+      pass->end_barrier.dst_access_mask |= dst_access_mask;
    } else {
-      if (dep->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
-         pass->subpasses[dst].start_barrier.src_stage_mask |= dep->srcStageMask;
-      pass->subpasses[dst].start_barrier.src_access_mask |= dep->srcAccessMask;
-      pass->subpasses[dst].start_barrier.dst_access_mask |= dep->dstAccessMask;
+      if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR)
+         pass->subpasses[dst].start_barrier.src_stage_mask |= src_stage_mask;
+      pass->subpasses[dst].start_barrier.src_access_mask |= src_access_mask;
+      pass->subpasses[dst].start_barrier.dst_access_mask |= dst_access_mask;
    }
 }