Mesa (main): radv: set export_clip_dists for the GS copy shader

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Module: Mesa
Branch: main
Commit: 89f1117c62c7afb3c19beb2af7ceaa1df947e2bf
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=89f1117c62c7afb3c19beb2af7ceaa1df947e2bf

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Sep 30 14:50:31 2021 +0200

radv: set export_clip_dists for the GS copy shader

This is needed for the next change to correctly compute the VS
output parameters from the shader info pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13119>

---

 src/amd/compiler/aco_instruction_selection_setup.cpp | 4 +++-
 src/amd/vulkan/radv_nir_to_llvm.c                    | 3 ++-
 src/amd/vulkan/radv_pipeline.c                       | 3 +++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 166ba5af819..a2166e5866d 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -1032,7 +1032,9 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c
    unsigned scratch_size = 0;
    if (program->stage == gs_copy_vs) {
       assert(shader_count == 1);
-      setup_vs_output_info(&ctx, shaders[0], false, true, &args->shader_info->vs.outinfo);
+      setup_vs_output_info(&ctx, shaders[0], false,
+                           args->shader_info->vs.outinfo.export_clip_dists,
+                           &args->shader_info->vs.outinfo);
    } else {
       for (unsigned i = 0; i < shader_count; i++) {
          nir_shader* nir = shaders[i];
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index a741c7f7250..2f38ddfe5f0 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2786,7 +2786,8 @@ ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
          radv_emit_streamout(ctx, stream);
 
       if (stream == 0) {
-         handle_vs_outputs_post(ctx, false, true, &ctx->args->shader_info->vs.outinfo);
+         handle_vs_outputs_post(ctx, false, ctx->args->shader_info->vs.outinfo.export_clip_dists,
+                                &ctx->args->shader_info->vs.outinfo);
       }
 
       LLVMBuildBr(ctx->ac.builder, end_bb);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 899b0e9ce7e..52ac8d1f2c0 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3565,6 +3565,9 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
       if (!pipeline_has_ngg) {
          struct radv_shader_info info = {0};
 
+         if (infos[MESA_SHADER_GEOMETRY].vs.outinfo.export_clip_dists)
+            info.vs.outinfo.export_clip_dists = true;
+
          radv_nir_shader_info_pass(device, nir[MESA_SHADER_GEOMETRY], pipeline->layout, pipeline_key,
                                    &info);
          info.wave_size = 64; /* Wave32 not supported. */