Mesa (main): freedreno/afuc: Avoid ubsan warns about shifting to the top bit of 'int'

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Module: Mesa
Branch: main
Commit: d5a80781aa1adf124aba98a453316b4fd8654bf8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5a80781aa1adf124aba98a453316b4fd8654bf8

Author: Emma Anholt <emma at anholt.net>
Date:   Thu Sep 23 13:56:27 2021 -0700

freedreno/afuc: Avoid ubsan warns about shifting to the top bit of 'int'

I think maybe it's being promoted to int due to the mismatched bitfield
sizes of the uint32_t values being referenced here?

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6360>

---

 src/freedreno/afuc/disasm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/freedreno/afuc/disasm.c b/src/freedreno/afuc/disasm.c
index d7b322a1022..0bf00ef8f4d 100644
--- a/src/freedreno/afuc/disasm.c
+++ b/src/freedreno/afuc/disasm.c
@@ -402,7 +402,7 @@ disasm_instr(uint32_t *instrs, unsigned pc)
          printf(" << %u", instr->movi.shift);
 
       if ((instr->movi.dst == REG_ADDR) && (instr->movi.shift >= 16)) {
-         uint32_t val = instr->movi.uimm << instr->movi.shift;
+         uint32_t val = (uint32_t)instr->movi.uimm << (uint32_t)instr->movi.shift;
          val &= ~0x40000;  /* b18 seems to be a flag */
 
          if ((val & 0x00ffffff) == 0) {
@@ -439,7 +439,7 @@ disasm_instr(uint32_t *instrs, unsigned pc)
          }
       }
 
-      print_gpu_reg(instr->movi.uimm << instr->movi.shift);
+      print_gpu_reg((uint32_t)instr->movi.uimm << (uint32_t)instr->movi.shift);
 
       break;
    }