Mesa (main): ac/surface: Add helper for checking if a surface supports DCC Image stores
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Sat Oct 2 23:21:41 UTC 2021
Module: Mesa
Branch: main
Commit: e6fcf65578738570fd03a3b487f0c12ce84a7aef
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6fcf65578738570fd03a3b487f0c12ce84a7aef
Author: Joshua Ashton <joshua at froggi.es>
Date: Fri Oct 1 22:52:03 2021 +0100
ac/surface: Add helper for checking if a surface supports DCC Image stores
We need to keep RADV and RadeonSI on the same page about this due to modifiers.
Signed-off-by: Joshua Ashton <joshua at froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13153>
---
src/amd/common/ac_surface.c | 22 ++++++++++++++++++++++
src/amd/common/ac_surface.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 58bd4b9e5a0..4771c01aba0 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -113,6 +113,28 @@ bool ac_modifier_supports_dcc_image_stores(uint64_t modifier)
AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier) == AMD_FMT_MOD_DCC_BLOCK_128B;
}
+
+bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class,
+ const struct radeon_surf *surf)
+{
+ /* DCC image stores is only available for GFX10+. */
+ if (chip_class < GFX10)
+ return false;
+
+ /* DCC image stores require the following settings:
+ * - INDEPENDENT_64B_BLOCKS = 0
+ * - INDEPENDENT_128B_BLOCKS = 1
+ * - MAX_COMPRESSED_BLOCK_SIZE = 128B
+ * - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used)
+ *
+ * The same limitations apply to SDMA compressed stores because
+ * SDMA uses the same DCC codec.
+ */
+ return !surf->u.gfx9.color.dcc.independent_64B_blocks &&
+ surf->u.gfx9.color.dcc.independent_128B_blocks &&
+ surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B;
+}
+
static
AddrSwizzleMode ac_modifier_gfx9_swizzle_mode(uint64_t modifier)
{
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 6a10e12247a..81e8ad2ca76 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -470,6 +470,9 @@ uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf,
void ac_surface_print_info(FILE *out, const struct radeon_info *info,
const struct radeon_surf *surf);
+bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class,
+ const struct radeon_surf *surf);
+
#ifdef AC_SURFACE_INCLUDE_NIR
nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
unsigned bpe, struct gfx9_meta_equation *equation,
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