Mesa (main): radeonsi: Use common DCC image store check

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Module: Mesa
Branch: main
Commit: e76956b9e01f95df79f568a7bd70ba40be22285b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e76956b9e01f95df79f568a7bd70ba40be22285b

Author: Joshua Ashton <joshua at froggi.es>
Date:   Fri Oct  1 22:53:43 2021 +0100

radeonsi: Use common DCC image store check

We need to keep RADV and RadeonSI on the same page about this due to modifiers.

Signed-off-by: Joshua Ashton <joshua at froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13153>

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 69d485a462e..f02855743a5 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -369,11 +369,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
                       * The same limitations apply to SDMA compressed stores because
                       * SDMA uses the same DCC codec.
                       */
-                     S_00A018_WRITE_COMPRESS_ENABLE(!tex->surface.u.gfx9.color.dcc.independent_64B_blocks &&
-                                                    tex->surface.u.gfx9.color.dcc.independent_128B_blocks &&
-                                                    tex->surface.u.gfx9.color.dcc.max_compressed_block_size ==
-                                                    V_028C78_MAX_BLOCK_SIZE_128B &&
-                                                    access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE);
+                     S_00A018_WRITE_COMPRESS_ENABLE(ac_surface_supports_dcc_image_stores(sscreen->info.chip_class, &tex->surface) &&
+                                                    (access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE));
       }
 
       state[7] = meta_va >> 16;