Mesa (main): intel/compiler: add missing line returns to logs

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Module: Mesa
Branch: main
Commit: 4e4560ab6f34e82dd04f169fee66339d9888ee9b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e4560ab6f34e82dd04f169fee66339d9888ee9b

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Sun Oct  3 15:58:36 2021 +0300

intel/compiler: add missing line returns to logs

In the upcoming intel_clc tool, we're allowing to print these messages
out and some of them just don't look right.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13165>

---

 src/intel/compiler/brw_fs.cpp             | 12 ++++++------
 src/intel/compiler/brw_fs_generator.cpp   |  2 +-
 src/intel/compiler/brw_vec4_generator.cpp |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 5cb72f86d67..7b6f65a8e1e 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -716,7 +716,7 @@ fs_visitor::limit_dispatch_width(unsigned n, const char *msg)
    } else {
       max_dispatch_width = MIN2(max_dispatch_width, n);
       brw_shader_perf_log(compiler, log_data,
-                          "Shader dispatch width limited to SIMD%d: %s",
+                          "Shader dispatch width limited to SIMD%d: %s\n",
                           n, msg);
    }
 }
@@ -9810,7 +9810,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
       v16->import_uniforms(v8);
       if (!v16->run_fs(allow_spilling, params->use_rep_send)) {
          brw_shader_perf_log(compiler, params->log_data,
-                             "SIMD16 shader failed to compile: %s",
+                             "SIMD16 shader failed to compile: %s\n",
                              v16->fail_msg);
       } else {
          simd16_cfg = v16->cfg;
@@ -9838,7 +9838,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
       v32->import_uniforms(v8);
       if (!v32->run_fs(allow_spilling, false)) {
          brw_shader_perf_log(compiler, params->log_data,
-                             "SIMD32 shader failed to compile: %s",
+                             "SIMD32 shader failed to compile: %s\n",
                              v32->fail_msg);
       } else {
          const performance &perf = v32->performance_analysis.require();
@@ -10212,7 +10212,7 @@ brw_compile_cs(const struct brw_compiler *compiler,
       const bool allow_spilling = generate_all || v == NULL;
       if (!v16->run_cs(allow_spilling)) {
          brw_shader_perf_log(compiler, params->log_data,
-                             "SIMD16 shader failed to compile: %s",
+                             "SIMD16 shader failed to compile: %s\n",
                              v16->fail_msg);
          if (!v) {
             assert(v8 == NULL);
@@ -10260,7 +10260,7 @@ brw_compile_cs(const struct brw_compiler *compiler,
       const bool allow_spilling = generate_all || v == NULL;
       if (!v32->run_cs(allow_spilling)) {
          brw_shader_perf_log(compiler, params->log_data,
-                             "SIMD32 shader failed to compile: %s",
+                             "SIMD32 shader failed to compile: %s\n",
                              v32->fail_msg);
          if (!v) {
             assert(v8 == NULL);
@@ -10456,7 +10456,7 @@ compile_single_bs(const struct brw_compiler *compiler, void *log_data,
       const bool allow_spilling = (v == NULL);
       if (!v16->run_bs(allow_spilling)) {
          brw_shader_perf_log(compiler, log_data,
-                             "SIMD16 shader failed to compile: %s",
+                             "SIMD16 shader failed to compile: %s\n",
                              v16->fail_msg);
          if (v == NULL) {
             assert(v8 == NULL);
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index f5acffd78e4..a1a74d14a78 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2804,7 +2804,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
                         "%d:%d spills:fills, %u sends, "
                         "scheduled with mode %s, "
                         "Promoted %u constants, "
-                        "compacted %d to %d bytes.",
+                        "compacted %d to %d bytes.\n",
                         _mesa_shader_stage_to_abbrev(stage),
                         dispatch_width, before_size / 16 - nop_count,
                         loop_count, perf.latency,
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index e1fb00fcfaa..5f880951e68 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -2266,7 +2266,7 @@ generate_code(struct brw_codegen *p,
    brw_shader_debug_log(compiler, log_data,
                         "%s vec4 shader: %d inst, %d loops, %u cycles, "
                         "%d:%d spills:fills, %u sends, "
-                        "compacted %d to %d bytes.",
+                        "compacted %d to %d bytes.\n",
                         stage_abbrev, before_size / 16,
                         loop_count, perf.latency, spill_count,
                         fill_count, send_count, before_size, after_size);