Mesa (main): gallium/ureg: Sort the input decls, too.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 8d6f738007b66e3f96d81196f39b8cd0bcff4374
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d6f738007b66e3f96d81196f39b8cd0bcff4374

Author: Emma Anholt <emma at anholt.net>
Date:   Thu Sep  9 12:52:00 2021 -0700

gallium/ureg: Sort the input decls, too.

Just like outputs, virglrenderer needs its inputs sorted.  Should be
harmless for other TGSI producers, and makes the declarations more
readable.

Acked-by: Gert Wollny <gert.wollny at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12800>

---

 src/gallium/auxiliary/tgsi/tgsi_ureg.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index 463c35362e2..eedba34cbc7 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -114,7 +114,7 @@ struct ureg_program
    bool supports_any_inout_decl_range;
    int next_shader_processor;
 
-   struct {
+   struct ureg_input_decl {
       enum tgsi_semantic semantic_name;
       unsigned semantic_index;
       enum tgsi_interpolate_mode interp;
@@ -1812,6 +1812,14 @@ emit_property(struct ureg_program *ureg,
    out[1].prop_data.Data = data;
 }
 
+static int
+input_sort(const void *in_a, const void *in_b)
+{
+   const struct ureg_input_decl *a = in_a, *b = in_b;
+
+   return a->first - b->first;
+}
+
 static int
 output_sort(const void *in_a, const void *in_b)
 {
@@ -1828,6 +1836,11 @@ static void emit_decls( struct ureg_program *ureg )
       if (ureg->properties[i] != ~0u)
          emit_property(ureg, i, ureg->properties[i]);
 
+   /* While not required by TGSI spec, virglrenderer has a dependency on the
+    * inputs being sorted.
+    */
+   qsort(ureg->input, ureg->nr_inputs, sizeof(ureg->input[0]), input_sort);
+
    if (ureg->processor == PIPE_SHADER_VERTEX) {
       for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
          if (ureg->vs_inputs[i/32] & (1u << (i%32))) {