Mesa (main): genxml: Drop bit 27 from RENDER_SURFACE_STATE::Surface Format

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Module: Mesa
Branch: main
Commit: 1f7e11a1900626e760ba0e5a6914ab1f7166f4b7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f7e11a1900626e760ba0e5a6914ab1f7166f4b7

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Tue Oct  5 16:42:58 2021 -0500

genxml: Drop bit 27 from RENDER_SURFACE_STATE::Surface Format

Bit 27 is the "ASTC Format" bit in the PRMs but we just extended the
Surface Format field by one bit and made sure all the ASTC formats have
that bit set.  Since Gfx12.5 doesn't support ASTC, we can drop that bit
from the field and this will cause GenXML packing functions to assert if
it's ever set.

Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>

---

 src/intel/genxml/gen125.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index a1b24843d30..c894fd68bcb 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -758,7 +758,7 @@
       <value name="VALIGN_8" value="2"/>
       <value name="VALIGN_16" value="3"/>
     </field>
-    <field name="Surface Format" start="18" end="27" type="uint"/>
+    <field name="Surface Format" start="18" end="26" type="uint"/>
     <field name="Surface Array" start="28" end="28" type="bool"/>
     <field name="Surface Type" start="29" end="31" type="uint">
       <value name="SURFTYPE_1D" value="0"/>