Mesa (main): anv: add missing transition handling bits

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Module: Mesa
Branch: main
Commit: ad9d95eee4065be9e54fba7da21f7df4583ddb8a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad9d95eee4065be9e54fba7da21f7df4583ddb8a

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Wed Nov 11 11:36:33 2020 +0200

anv: add missing transition handling bits

New access flags & pipeline stages got added for transform feedback
and we missed handling them.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 36ee2fd61c8f ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9045>

---

 src/intel/vulkan/anv_private.h     | 21 +++++++++++++++------
 src/intel/vulkan/genX_cmd_buffer.c |  3 ++-
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index c9ee3b853ef..09567490f30 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2596,6 +2596,14 @@ anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
          pipe_bits |= ANV_PIPE_FLUSH_BITS;
          pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
          break;
+      case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
+      case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
+         /* We're transitioning a buffer written either from VS stage or from
+          * the command streamer (see CmdEndTransformFeedbackEXT), we just
+          * need to stall the CS.
+          */
+         pipe_bits |= ANV_PIPE_CS_STALL_BIT;
+         break;
       default:
          break; /* Nothing to do */
       }
@@ -2675,18 +2683,19 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
          pipe_bits |= ANV_PIPE_FLUSH_BITS;
          break;
       case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
-         /* Transitioning a buffer for conditional rendering. We'll load the
-          * content of this buffer into HW registers using the command
-          * streamer, so we need to stall the command streamer to make sure
-          * any in-flight flush operations have completed. Needs tile cache 
-          * and data cache flush because command stream isn't L3 coherent yet.
+      case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT:
+         /* Transitioning a buffer for conditional rendering or transform
+          * feedback. We'll load the content of this buffer into HW registers
+          * using the command streamer, so we need to stall the command
+          * streamer , so we need to stall the command streamer to make sure
+          * any in-flight flush operations have completed.
           */
          pipe_bits |= ANV_PIPE_CS_STALL_BIT;
          pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
          pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
          break;
       case VK_ACCESS_HOST_READ_BIT:
-         /* We're transitioning a buffer that was written by CPU.  Flush 
+         /* We're transitioning a buffer that was written by CPU.  Flush
           * all the caches.
           */
          pipe_bits |= ANV_PIPE_FLUSH_BITS;
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 894e396738b..f2992b561ef 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -6879,7 +6879,8 @@ void genX(CmdEndConditionalRenderingEXT)(
     VK_PIPELINE_STAGE_TRANSFER_BIT | \
     VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
     VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
-    VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
+    VK_PIPELINE_STAGE_ALL_COMMANDS_BIT | \
+    VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)
 
 void genX(CmdSetEvent)(
     VkCommandBuffer                             commandBuffer,