Mesa (main): radv: determine if a shader uses indirect descriptors from the SGPR loc

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Module: Mesa
Branch: main
Commit: 113ce215280bcc46b7652963317c5b9e7311e91f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=113ce215280bcc46b7652963317c5b9e7311e91f

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Sep 28 10:44:45 2021 +0200

radv: determine if a shader uses indirect descriptors from the SGPR loc

If the SGPR loc is declared, the shader needs indirect descriptor sets.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13149>

---

 src/amd/compiler/aco_instruction_selection.cpp |  4 +++-
 src/amd/vulkan/radv_nir_to_llvm.c              |  4 +++-
 src/amd/vulkan/radv_pipeline.c                 | 12 ++++++++++--
 src/amd/vulkan/radv_shader.h                   |  1 -
 src/amd/vulkan/radv_shader_args.c              |  2 --
 5 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 660e259dbbb..f38344249f3 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -5317,7 +5317,9 @@ visit_load_tess_coord(isel_context* ctx, nir_intrinsic_instr* instr)
 Temp
 load_desc_ptr(isel_context* ctx, unsigned desc_set)
 {
-   if (ctx->program->info->need_indirect_descriptor_sets) {
+   struct radv_userdata_locations *user_sgprs_locs = &ctx->program->info->user_sgprs_locs;
+
+   if (user_sgprs_locs->shader_data[AC_UD_INDIRECT_DESCRIPTOR_SETS].sgpr_idx != -1) {
       Builder bld(ctx->program, ctx->block);
       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
       Operand off = bld.copy(bld.def(s1), Operand::c32(desc_set << 2));
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index bbe7d6999b2..980b54f43cc 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -111,8 +111,10 @@ create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module, LLVMBuil
 static void
 load_descriptor_sets(struct radv_shader_context *ctx)
 {
+   struct radv_userdata_locations *user_sgprs_locs = &ctx->args->shader_info->user_sgprs_locs;
    uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
-   if (ctx->args->shader_info->need_indirect_descriptor_sets) {
+
+   if (user_sgprs_locs->shader_data[AC_UD_INDIRECT_DESCRIPTOR_SETS].sgpr_idx != -1) {
       LLVMValueRef desc_sets = ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
       while (mask) {
          int i = u_bit_scan(&mask);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index edc21068a9a..69510fdbf53 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -5449,6 +5449,14 @@ radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
    return NULL;
 }
 
+static bool
+radv_shader_need_indirect_descriptor_sets(struct radv_pipeline *pipeline, gl_shader_stage stage)
+{
+   struct radv_userdata_info *loc =
+      radv_lookup_user_sgpr(pipeline, stage, AC_UD_INDIRECT_DESCRIPTOR_SETS);
+   return loc->sgpr_idx != -1;
+}
+
 static void
 radv_pipeline_init_shader_stages_state(struct radv_pipeline *pipeline)
 {
@@ -5460,7 +5468,7 @@ radv_pipeline_init_shader_stages_state(struct radv_pipeline *pipeline)
 
       if (pipeline->shaders[i]) {
          pipeline->need_indirect_descriptor_sets |=
-            pipeline->shaders[i]->info.need_indirect_descriptor_sets;
+            radv_shader_need_indirect_descriptor_sets(pipeline, i);
       }
    }
 
@@ -5793,7 +5801,7 @@ radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache,
    pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(
       pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
    pipeline->need_indirect_descriptor_sets |=
-      pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
+      radv_shader_need_indirect_descriptor_sets(pipeline, MESA_SHADER_COMPUTE);
    radv_pipeline_init_scratch(device, pipeline);
 
    radv_compute_generate_pm4(pipeline);
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index fc1752c3718..f6c2f8129e2 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -231,7 +231,6 @@ struct radv_shader_info {
    unsigned num_user_sgprs;
    unsigned num_input_sgprs;
    unsigned num_input_vgprs;
-   bool need_indirect_descriptor_sets;
    bool is_ngg;
    bool is_ngg_passthrough;
    bool has_ngg_culling;
diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c
index 705bcc8d43b..8017787deb8 100644
--- a/src/amd/vulkan/radv_shader_args.c
+++ b/src/amd/vulkan/radv_shader_args.c
@@ -393,8 +393,6 @@ set_global_input_locs(struct radv_shader_args *args, const struct user_sgpr_info
       }
    } else {
       set_loc_shader_ptr(args, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx);
-
-      args->shader_info->need_indirect_descriptor_sets = true;
    }
 
    if (args->ac.push_constants.used) {