Mesa (main): radv: remove unnecessary radv_shader_info:num_inline_push_consts
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Fri Oct 8 12:08:32 UTC 2021
Module: Mesa
Branch: main
Commit: a6298b1bc9fe53d46af19d6509255b327898a2df
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6298b1bc9fe53d46af19d6509255b327898a2df
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 1 15:59:05 2021 +0200
radv: remove unnecessary radv_shader_info:num_inline_push_consts
This can be determined directly from the user SGPR loc.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13149>
---
src/amd/common/ac_shader_args.h | 1 -
src/amd/compiler/aco_instruction_selection.cpp | 6 +++++-
src/amd/llvm/ac_nir_to_llvm.c | 7 ++++++-
src/amd/vulkan/radv_cmd_buffer.c | 13 +++++--------
src/amd/vulkan/radv_shader.h | 1 -
src/amd/vulkan/radv_shader_args.c | 14 +++++++-------
6 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/src/amd/common/ac_shader_args.h b/src/amd/common/ac_shader_args.h
index 4f2dba2ba28..270682f42d1 100644
--- a/src/amd/common/ac_shader_args.h
+++ b/src/amd/common/ac_shader_args.h
@@ -139,7 +139,6 @@ struct ac_shader_args {
/* Vulkan only */
struct ac_arg push_constants;
struct ac_arg inline_push_consts[AC_MAX_INLINE_PUSH_CONSTS];
- unsigned num_inline_push_consts;
unsigned base_inline_push_consts;
struct ac_arg view_index;
struct ac_arg sbt_descriptors;
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 17ae895452d..ca85807ac17 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -5490,9 +5490,13 @@ visit_load_push_constant(isel_context* ctx, nir_intrinsic_instr* instr)
nir_const_value* index_cv = nir_src_as_const_value(instr->src[0]);
if (index_cv && instr->dest.ssa.bit_size == 32) {
+ struct radv_userdata_info *loc =
+ &ctx->args->shader_info->user_sgprs_locs.shader_data[AC_UD_INLINE_PUSH_CONSTANTS];
unsigned start = (offset + index_cv->u32) / 4u;
+ unsigned num_inline_push_consts = loc->sgpr_idx != -1 ? loc->num_sgprs : 0;
+
start -= ctx->args->shader_info->min_push_constant_used / 4;
- if (start + count <= ctx->args->ac.num_inline_push_consts) {
+ if (start + count <= num_inline_push_consts) {
std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(
aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index 3ea47221b7a..d4945527b25 100644
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -1644,7 +1644,12 @@ static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx, nir_int
offset -= ctx->args->base_inline_push_consts;
- unsigned num_inline_push_consts = ctx->args->num_inline_push_consts;
+ unsigned num_inline_push_consts = 0;
+ for (unsigned i = 0; i < ARRAY_SIZE(ctx->args->inline_push_consts); i++) {
+ if (ctx->args->inline_push_consts[i].used)
+ num_inline_push_consts++;
+ }
+
if (offset + count <= num_inline_push_consts) {
LLVMValueRef *const push_constants = alloca(num_inline_push_consts * sizeof(LLVMValueRef));
for (unsigned i = 0; i < num_inline_push_consts; i++)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ab6b32f873b..7027487b8e8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -993,19 +993,17 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline,
- gl_shader_stage stage, int idx, int count, uint32_t *values)
+ gl_shader_stage stage, int idx, uint32_t *values)
{
struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
uint32_t base_reg = pipeline->user_data_0[stage];
if (loc->sgpr_idx == -1)
return;
- assert(loc->num_sgprs == count);
+ radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 2 + loc->num_sgprs);
- radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 2 + count);
-
- radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
- radeon_emit_array(cmd_buffer->cs, values, count);
+ radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs);
+ radeon_emit_array(cmd_buffer->cs, values, loc->num_sgprs);
}
static void
@@ -2886,9 +2884,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag
need_push_constants |= radv_shader_loads_push_constants(pipeline, stage);
uint8_t base = shader->info.min_push_constant_used / 4;
- uint8_t count = shader->info.num_inline_push_consts;
- radv_emit_inline_push_consts(cmd_buffer, pipeline, stage, AC_UD_INLINE_PUSH_CONSTANTS, count,
+ radv_emit_inline_push_consts(cmd_buffer, pipeline, stage, AC_UD_INLINE_PUSH_CONSTANTS,
(uint32_t *)&cmd_buffer->push_constants[base * 4]);
}
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 9c4d405fe6d..4657ee6235c 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -219,7 +219,6 @@ struct radv_shader_info {
uint8_t max_push_constant_used;
bool has_only_32bit_push_constants;
bool has_indirect_push_constants;
- uint8_t num_inline_push_consts;
uint32_t desc_set_used_mask;
bool needs_multiview_view_index;
bool uses_invocation_id;
diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c
index 5e8ad656bb4..48a57dc39d1 100644
--- a/src/amd/vulkan/radv_shader_args.c
+++ b/src/amd/vulkan/radv_shader_args.c
@@ -70,6 +70,7 @@ set_loc_desc(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx)
struct user_sgpr_info {
bool indirect_all_descriptor_sets;
uint8_t remaining_sgprs;
+ unsigned num_inline_push_consts;
};
static bool
@@ -152,16 +153,16 @@ allocate_inline_push_consts(struct radv_shader_args *args, struct user_sgpr_info
/* Check if the number of user SGPRs is large enough. */
if (num_push_consts < remaining_sgprs) {
- args->shader_info->num_inline_push_consts = num_push_consts;
+ user_sgpr_info->num_inline_push_consts = num_push_consts;
} else {
- args->shader_info->num_inline_push_consts = remaining_sgprs;
+ user_sgpr_info->num_inline_push_consts = remaining_sgprs;
}
/* Clamp to the maximum number of allowed inlined push constants. */
- if (args->shader_info->num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
- args->shader_info->num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
+ if (user_sgpr_info->num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
+ user_sgpr_info->num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
- if (args->shader_info->num_inline_push_consts == num_push_consts &&
+ if (user_sgpr_info->num_inline_push_consts == num_push_consts &&
!args->shader_info->loads_dynamic_offsets) {
/* Disable the default push constants path if all constants are
* inlined and if shaders don't use dynamic descriptors.
@@ -265,10 +266,9 @@ declare_global_input_sgprs(struct radv_shader_args *args,
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_PTR, &args->ac.push_constants);
}
- for (unsigned i = 0; i < args->shader_info->num_inline_push_consts; i++) {
+ for (unsigned i = 0; i < user_sgpr_info->num_inline_push_consts; i++) {
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.inline_push_consts[i]);
}
- args->ac.num_inline_push_consts = args->shader_info->num_inline_push_consts;
args->ac.base_inline_push_consts = args->shader_info->min_push_constant_used / 4;
if (args->shader_info->so.num_outputs) {
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