Mesa (main): ac/surface: enable better display DCC for chips newer than Yellow Carp

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Module: Mesa
Branch: main
Commit: 84d0f54e75a440d3149e68e92a51685d04687c68
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=84d0f54e75a440d3149e68e92a51685d04687c68

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed Oct  6 02:23:43 2021 -0400

ac/surface: enable better display DCC for chips newer than Yellow Carp

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13214>

---

 src/amd/common/ac_surface.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index ca03633e1f0..121093979b3 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -2169,8 +2169,13 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
                surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
             }
 
-            /* Use 64 && 128 for the non-modifier path for compatibility. */
-            if (info->chip_class >= GFX10_3) {
+            if ((info->chip_class >= GFX10_3 && info->family <= CHIP_YELLOW_CARP) ||
+                /* Newer chips will skip this when possible to get better performance.
+                 * This is also possible for other gfx10.3 chips, but is disabled for
+                 * interoperability between different Mesa versions.
+                 */
+                (info->family > CHIP_YELLOW_CARP &&
+                 gfx10_DCN_requires_independent_64B_blocks(info, config))) {
                surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
                surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
                surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;